PIC18F45J11-I/ML Microchip Technology, PIC18F45J11-I/ML Datasheet - Page 269
![IC PIC MCU FLASH 32K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F45J11-I/ML
Manufacturer Part Number
PIC18F45J11-I/ML
Description
IC PIC MCU FLASH 32K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F45J11-I/ML
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC18
No. Of I/o's
22
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
No. Of Pwm Channels
2
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183032, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
A/d Bit Size
10 bit
A/d Channels Available
13
Height
0.88 mm
Length
8 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.15 V
Width
8 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 269 of 528
- Download datasheet (8Mb)
18.3.2
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
• Clock Edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP module consists of a transmit/receive shift
register (SSPxSR) and a buffer register (SSPxBUF).
The SSPxSR shifts the data in and out of the device,
MSb first. The SSPxBUF holds the data that was written
to the SSPxSR until the received data is ready. Once the
8 bits of data have been received, that byte is moved to
the SSPxBUF register. Then, the Buffer Full (BF) detect
bit (SSPxSTAT<0>) and the interrupt flag bit, SSPxIF,
are set. This double-buffering of the received data
(SSPxBUF) allows the next byte to start reception before
reading the data that was just received.
Any write to the SSPxBUF register during transmis-
sion/reception of data will be ignored and the Write
Collision Detect bit, WCOL (SSPxCON1<7>), will be set.
User software must clear the WCOL bit so that it can be
determined if the following write(s) to the SSPxBUF
register completed successfully.
EXAMPLE 18-1:
© 2009 Microchip Technology Inc.
LOOP
output time)
SCKx)
Note:
BTFSS
BRA
MOVF
MOVWF
MOVF
MOVWF
OPERATION
When the application software is expecting
to receive valid data, the SSPxBUF should
be read before the next byte of transfer
data is written to the SSPxBUF. Application
software should follow this process even
when the current contents of SSPxBUF
are not important.
SSP1STAT, BF
LOOP
SSP1BUF, W
RXDATA
TXDATA, W
SSP1BUF
LOADING THE SSP1BUF (SSP1SR) REGISTER
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSP1BUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
PIC18F46J11 FAMILY
The Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to be
used, then software polling can be done to ensure that a
write collision does not occur.
Example 18-1 provides the loading of the SSPxBUF
(SSPxSR) for data transmission.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
18.3.3
The drivers for the SDOx output and SCKx clock pins
can be optionally configured as open-drain outputs.
This feature allows the voltage level on the pin to be
pulled to a higher level through an external pull-up
resistor, provided the SDOx or SCKx pin is not multi-
plexed with an ANx analog function. This allows the
output to communicate with external circuits without the
need for additional level shifters. For more information,
see Section 9.1.4 “Open-Drain Outputs”.
The open-drain output option is controlled by the
SPI2OD and SPI1OD bits (ODCON3<1:0>). Setting an
SPIxOD bit configures both SDOx and SCKx pins for the
corresponding open-drain operation.
OPEN-DRAIN OUTPUT OPTION
DS39932C-page 269
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