PIC18F45J11-I/ML Microchip Technology, PIC18F45J11-I/ML Datasheet - Page 212
![IC PIC MCU FLASH 32K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F45J11-I/ML
Manufacturer Part Number
PIC18F45J11-I/ML
Description
IC PIC MCU FLASH 32K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F45J11-I/ML
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC18
No. Of I/o's
22
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
No. Of Pwm Channels
2
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183032, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
A/d Bit Size
10 bit
A/d Channels Available
13
Height
0.88 mm
Length
8 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.15 V
Width
8 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (8Mb)
PIC18F46J11 FAMILY
14.2
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
FIGURE 14-1:
DS39932C-page 212
T3G
From Timer0
Overflow
From Timer2
Match PR2
Note 1:
T3GSS<1:0>
Timer3 Operation
2:
3:
T3GPOL
ST Buffer is high-speed type when using T3CKI.
Timer3 register increments on rising edge.
Synchronize does not operate while in Sleep.
Set Flag bit,
TMR3IF, on
Overflow
TIMER3 BLOCK DIAGRAM
00
10
01
TMR3ON
T3GTM
TMR3H
TMR3
T3G_IN
(2)
D
R
CK
TMR3L
Q
Q
TMR3CS<1:0>
0
1
T3GGO/T3DONE
Q
Internal
Internal
F
T3CKI
OSC
Clock
Clock
F
OSC
EN
/4
D
external clock from the T3CKI pin (on the rising edge
The operating mode is determined by the clock select
bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits
are cleared (= 00), Timer3 increments on every internal
instruction cycle (F
Timer3 clock source is the system clock (F
when it is ‘10’, Timer3 works as a counter from the
after the first falling edge) or the Timer1 oscillator.
Single Pulse
Acq. Control
10
01
00
T3CLK
T3GSPM
T3CKPS<1:0>
T3SYNC
Prescaler
1, 2, 4, 8
TMR3ON
0
1
2
0
1
Internal
OSC
F
Clock
OSC
T3GVAL
TMR3GE
/4). When TMR3CSx = 01, the
/2
© 2009 Microchip Technology Inc.
Q1
Synchronized
Synchronize
Interrupt
Clock Input
D
EN
det
det
Sleep Input
Q
(3)
Set
TMR3GIF
Data Bus
RD
T3GCON
OSC
), and
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