PIC18F45J11-I/ML Microchip Technology, PIC18F45J11-I/ML Datasheet - Page 166
![IC PIC MCU FLASH 32K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F45J11-I/ML
Manufacturer Part Number
PIC18F45J11-I/ML
Description
IC PIC MCU FLASH 32K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F45J11-I/ML
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC18
No. Of I/o's
22
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
No. Of Pwm Channels
2
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183032, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
A/d Bit Size
10 bit
A/d Channels Available
13
Height
0.88 mm
Length
8 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.15 V
Width
8 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 166 of 528
- Download datasheet (8Mb)
PIC18F46J11 FAMILY
10.1
The PMP module has a total of 14 Special Function
Registers (SFRs) for its operation, plus one additional
register to set configuration options. Of these, eight
registers are used for control and six are used for PMP
data transfer.
10.1.1
The eight PMP Control registers are:
• PMCONH and PMCONL
• PMMODEH and PMMODEL
• PMSTATL and PMSTATH
• PMEH and PMEL
REGISTER 10-1:
DS39932C-page 166
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4-3
bit 2
bit 1
bit 0
Note 1:
PMPEN
R/W-0
Module Registers
This register is only available in 44-pin devices.
CONTROL REGISTERS
PMPEN: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
Unimplemented: Read as ‘0’
PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins (only eight bits of address are
00 = Address and data appear on separate pins (only eight bits of address are available in this mode)
PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
U-0
—
available in this mode)
PMCONH: PARALLEL PORT CONTROL REGISTER HIGH BYTE (BANKED F5Fh)
W = Writable bit
‘1’ = Bit is set
PSIDL
R/W-0
ADRMUX1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADRMUX0
R/W-0
The
Register 10-2) control basic module operations, includ-
ing turning the module on or off. They also configure
address multiplexing and control strobe configuration.
The
Register 10-4) configure the various Master and Slave
modes, the data width and interrupt generation.
The PMEH and PMEL registers (Register 10-5 and
Register 10-6) configure the module’s operation at the
hardware (I/O pin) level.
The
Register 10-6) provide status flags for the module’s
input and output buffers, depending on the operating
mode.
PMMODE
PMCON
PMSTAT
PTBEEN
R/W-0
registers
registers
registers
© 2009 Microchip Technology Inc.
x = Bit is unknown
PTWREN
R/W-0
(Register 10-1
(Register 10-5
(Register 10-3
PTRDEN
R/W-0
bit 0
and
and
and
(1)
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