PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 150
![IC PIC MCU FLASH 48KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F66J15-I/PT
Manufacturer Part Number
PIC18F66J15-I/PT
Description
IC PIC MCU FLASH 48KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F85J10-IPT.pdf
(410 pages)
4.PIC18F85J10-IPT.pdf
(10 pages)
5.PIC18F85J10-IPT.pdf
(10 pages)
6.PIC18F85J10-IPT.pdf
(8 pages)
7.PIC18F66J15-IPT.pdf
(400 pages)
Specifications of PIC18F66J15-I/PT
Program Memory Type
FLASH
Program Memory Size
96KB (48K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
50
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F66J15-I/PT
Manufacturer:
TI/CC
Quantity:
1 500
Company:
Part Number:
PIC18F66J15-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F66J15-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F85J10-IPT PDF datasheet #3
- PIC18F85J10-IPT PDF datasheet #4
- PIC18F85J10-IPT PDF datasheet #5
- PIC18F85J10-IPT PDF datasheet #6
- PIC18F66J15-IPT PDF datasheet #7
- Current page: 150 of 400
- Download datasheet (7Mb)
PIC18F87J10
11.1
Timer0 can operate as either a timer or a counter. The
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 11.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit, T0SE (T0CON<4>); clearing this bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 11-1:
FIGURE 11-2:
DS39663D-page 148
T0CKI pin
Note:
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
Timer0 Operation
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0SE
T0CS
T0PS2:T0PS0
PSA
F
OSC
T0SE
T0CS
T0PS2:T0PS0
PSA
/4
F
OSC
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
/4
0
1
0
1
Programmable
Prescaler
Programmable
3
Prescaler
3
1
0
Preliminary
1
0
(2 T
Sync with
Internal
Clocks
CY
(2 T
Delay)
Sync with
Internal
Clocks
CY
internal phase clock (T
synchronization and the onset of incrementing the
timer/counter.
11.2
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0 which is not directly readable nor writ-
able (refer to Figure 11-2). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
Delay)
Timer0 Reads and Writes in
16-bit Mode
TMR0L
8
8
TMR0L
8
8
OSC
© 2006 Microchip Technology Inc.
High Byte
TMR0H
TMR0
8
). There is a delay between
8
Set
TMR0IF
on Overflow
Internal Data Bus
8
Set
TMR0IF
on Overflow
Read TMR0L
Write TMR0L
Internal Data Bus
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