PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 101
![IC PIC MCU FLASH 48KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F66J15-I/PT
Manufacturer Part Number
PIC18F66J15-I/PT
Description
IC PIC MCU FLASH 48KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F85J10-IPT.pdf
(410 pages)
4.PIC18F85J10-IPT.pdf
(10 pages)
5.PIC18F85J10-IPT.pdf
(10 pages)
6.PIC18F85J10-IPT.pdf
(8 pages)
7.PIC18F66J15-IPT.pdf
(400 pages)
Specifications of PIC18F66J15-I/PT
Program Memory Type
FLASH
Program Memory Size
96KB (48K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
50
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F66J15-I/PT
Manufacturer:
TI/CC
Quantity:
1 500
Company:
Part Number:
PIC18F66J15-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F66J15-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F85J10-IPT PDF datasheet #3
- PIC18F85J10-IPT PDF datasheet #4
- PIC18F85J10-IPT PDF datasheet #5
- PIC18F85J10-IPT PDF datasheet #6
- PIC18F66J15-IPT PDF datasheet #7
- Current page: 101 of 400
- Download datasheet (7Mb)
7.7
In 8-bit Data Width mode, the external memory bus
operates only in Multiplexed mode; that is, data shares
the 8 Least Significant bits of the address bus.
Figure 7-6 shows an example of 8-bit Multiplexed
mode for 80-pin devices. This mode is used for a single
8-bit memory connected for 16-bit operation. The
instructions will be fetched as two 8-bit bytes on a
shared data/address bus. The two bytes are sequen-
tially fetched within one instruction cycle (T
Therefore, the designer must choose external memory
devices according to timing calculations based on
1/2 T
ory speed selection, glue logic propagation delay times
must be considered, along with setup and hold times.
The Address Latch Enable (ALE) pin indicates that the
address bits AD<15:0> are available on the external
memory interface bus. The Output Enable signal (OE)
FIGURE 7-6:
© 2006 Microchip Technology Inc.
CY
(2 times the instruction rate). For proper mem-
8-bit Mode
Note 1:
2:
PIC18F8XJ10
Upper order address bits are only used for 20-bit address width. The upper AD byte is used for all
address widths except 8-bit.
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
AD<15:8>
A<19:16>
8-BIT MULTIPLEXED MODE EXAMPLE
AD<7:0>
WRL
ALE
BA0
CE
OE
(1)
(1)
CY
Preliminary
).
373
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruc-
tion word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing. It is inactive
(asserted high) whenever the device is in Sleep mode.
This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate level of the BA0
control line is strobed on the LSb of the TBLPTR.
D<7:0>
A<19:0>
D<15:8>
Address Bus
Data Bus
Control Lines
PIC18F87J10
A0
OE
A<x:1>
D<7:0>
CE
WR
DS39663D-page 99
(2)
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