PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC18F66J15-I/PT
• Description: IC PIC MCU FLASH 48KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J15-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J10 FAMILY
3. Module: MSSP
4. Module: MSSP
TABLE 1:
DS80246B-page 2
Note 1:
In SPI mode, the Buffer Full bit (BF in SSPxSTAT
register), the Write Collision Detect bit (WCOL in
SSPxCON1) and the Receive Overflow Indicator
bit (SSPOV in SSPxCON1) are not reset upon
disabling the SPI module (by clearing the SSPEN
bit in SSPxCON1 register).
For example, if SSPxBUF is full (BF bit is set) and
the MSSP module is disabled, and then re-
enabled, the BF bit will remain set. In SPI Slave
mode, a subsequent write to SSPxBUF will result
in a write collision; or in SPI Slave mode, if a new
byte is received, a receive overflow will occur.
Work around
Ensure that if the buffer is full, SSPxBUF is read
(thus clearing the BF flag) before disabling the
MSSP module. Also, ensure that WCOL is clear
before disabling the MSSP module. If the module
was configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.
In its current implementation, the I
mode operates as follows:
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
I
2
2
C™ interface does not conform to the 400 kHz I
C™ CLOCK RATE w/BRG
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
F
CY
2
C™ Master
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
* 2
2
Note:
C specification (which applies to rates greater than
SSPADD = INT((F
a)
b)
Date Codes that pertain to this issue:
All engineering and production devices.
The Baud Rate Generator for I
mode is slower than the rates specified in
Table 17-3 of the Device Data Sheet.
For this revision of silicon, use the values
shown in Table 1 in place of those shown in
Table 17-3 of the Device Data Sheet. The
differences are shown in bold text.
Use the following formula in place of the
one shown in Register 17-4 (SSPCON1) of
the Device Data Sheet for bit description
SSPM3:SSPM0 = 1000.
The I
the accuracy of the bus frequency is not
critical.
BRG Value
2
0Eh
15h
59h
05h
08h
23h
01h
08h
00h
C bus is a synchronous protocol, so
CY
/F
© 2006 Microchip Technology Inc.
SCL
) – (F
(2 Rollovers of BRG)
CY
/1.111 MHz)) – 1
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
2
F
C in Master
SCL
(1)
(1)
(1)
(1)