PIC18LF44J50-I/PT Microchip Technology, PIC18LF44J50-I/PT Datasheet - Page 310
![IC PIC MCU FLASH 16K 2V 44-TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF44J50-I/PT
Manufacturer Part Number
PIC18LF44J50-I/PT
Description
IC PIC MCU FLASH 16K 2V 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF44J50-I/PT
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF44J50-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F46J50 FAMILY
18.5.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The BRG
then counts for one rollover period (T
pin is deasserted (pulled high). When the SCLx pin is
sampled high (clock arbitration), the BRG counts for
T
ACKEN bit is automatically cleared, the BRG is turned
off and the MSSP module then goes into an inactive
state (Figure 18-25).
18.5.12.1
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 18-25:
FIGURE 18-26:
DS39931C-page 310
BRG
Note:
Note:
; the SCLx pin is then pulled low. Following this, the
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SCLx
SDAx
T
T
BRG
BRG
Sequence
Write to SSPxCON2,
SSPxIF
= one Baud Rate Generator period.
SDAx
SCLx
= one Baud Rate Generator period.
Falling edge of
9th clock
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
Acknowledge sequence starts here,
ACK
SSPxIF set at
the end of receive
set PEN
Enable
ACKEN = 1, ACKDT = 0
write to SSPxCON2,
BRG
T
) and the SCLx
T
bit,
BRG
BRG
SDAx asserted low before rising edge of clock
to set up Stop condition
8
D0
ACKEN
T
SCLx brought high after T
BRG
Cleared in
software
P
T
BRG
SCLx = 1 for T
after SDAx sampled high. P bit (SSPxSTAT<4>) is set
T
BRG
ACK
18.5.13
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the BRG is reloaded and
counts down to 0. When the BRG times out, the SCLx
pin will be brought high and one Baud Rate Generator
rollover count (T
deasserted. When the SDAx pin is sampled high while
SCLx is high, the Stop bit (SSPxSTAT<4>) is set. A
T
set (Figure 18-26).
18.5.13.1
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
BRG
PEN bit (SSPxCON2<2>) is cleared by
T
BRG
hardware and the SSPxIF bit is set
later, the PEN bit is cleared and the SSPxIF bit is
9
BRG
SSPxIF set at the end
of Acknowledge sequence
BRG
, followed by SDAx = 1 for T
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
BRG
) later, the SDAx pin will be
© 2009 Microchip Technology Inc.
Cleared in
software
BRG
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