PIC18LF44J50-I/PT Microchip Technology, PIC18LF44J50-I/PT Datasheet - Page 139
![IC PIC MCU FLASH 16K 2V 44-TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF44J50-I/PT
Manufacturer Part Number
PIC18LF44J50-I/PT
Description
IC PIC MCU FLASH 16K 2V 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF44J50-I/PT
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF44J50-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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9.5
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt Trigger
input buffers. Each pin is individually configurable as an
input or output.
TABLE 9-9:
© 2009 Microchip Technology Inc.
RD0/PMD0/
SCL2
RD1/PMD1/
SDA2
RD2/PMD2/
RP19
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I
Note:
Note:
Pin
PORTD, TRISD and LATD
Registers
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PORTD is available only in 44-pin devices.
On a POR, these pins are configured as
digital inputs.
PORTD I/O SUMMARY
Function
PMD0
PMD1
PMD2
SCL2
SDA2
RP19
RD0
RD1
RD2
Setting
TRIS
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
ST/TTL Parallel Master Port data in.
Type
SMB
SMB
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
I
I
I/O
ST
ST
ST
ST
2
2
C/
C/
PORTD<0> data input.
LATD<0> data output.
Parallel Master Port data out.
I
module setting.
I
PORTD<1> data input.
LATD<1> data output.
Parallel Master Port data in.
Parallel Master Port data out.
I
ule setting.
I
PORTD<2> data input.
LATD<2> data output.
Parallel Master Port data in.
Parallel Master Port data out.
Remappable peripheral pin 19 input.
Remappable peripheral pin 19 output.
2
2
2
2
C clock output (MSSP2 module); takes priority over port data.
C™ clock input (MSSP2 module); input type depends on
C data input (MSSP2 module); input type depends on mod-
C data output (MSSP2 module); takes priority over port data.
PIC18F46J50 FAMILY
EXAMPLE 9-5:
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by setting bit, RDPU (PORTE<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
POR. The integrated weak pull-ups consist of a semi-
conductor structure similar to, but somewhat different,
from a discrete resistor. On an unloaded I/O pin, the
weak pull-ups are intended to provide logic high indica-
tion, but will not necessarily pull the pin all the way to
V
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB.
CLRF
CLRF
MOVLW 0CFh
MOVWF TRISD
DD
levels.
PORTD
LATD
Description
;
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
;
;
INITIALIZING PORTD
Initialize PORTD by
RD<5:4> as outputs
RD<7:6> as inputs
2
C/SMB = I
DS39931C-page 139
2
C/SMBus
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