PIC18LF44J50-I/PT Microchip Technology, PIC18LF44J50-I/PT Datasheet - Page 133
![IC PIC MCU FLASH 16K 2V 44-TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF44J50-I/PT
Manufacturer Part Number
PIC18LF44J50-I/PT
Description
IC PIC MCU FLASH 16K 2V 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF44J50-I/PT
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF44J50-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 9-5:
© 2009 Microchip Technology Inc.
RB0/AN12/
INT0/RP3
RB1/AN10/
RTCC/RP4
RB2/AN8/
CTEDG1/VMO/
REFO/RP5
RB3/AN9/
CTEDG2/
PMA2/VPO/
RP6
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
Pin
2:
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog
inputs by default when PBADEN is set and digital inputs when PBADEN is cleared.
All other pin functions are disabled when ICSP™ or ICD are enabled.
PORTB I/O SUMMARY
Function
CTEDG1
CTEDG2
RTCC
REFO
PMA2
AN12
AN10
VMO
INT0
VPO
RB0
RP3
RB1
RP4
RB2
AN8
RP5
RB3
AN9
RP6
Setting
TRIS
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
0
1
1
1
0
0
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
TTL
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
PORTB<0> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
LATB<0> data output; not affected by analog input.
A/D input channel 12.
External interrupt 0 input.
Remappable peripheral pin 3 input.
Remappable peripheral pin 3 output.
PORTB<1> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
LATB<1> data output; not affected by analog input.
A/D input channel 10.
Asynchronous serial transmit data output (USART module).
Remappable peripheral pin 4 input.
Remappable peripheral pin 4 output.
PORTB<2> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
LATB<2> data output; not affected by analog input.
A/D input channel 8.
CTMU Edge 1 input.
External USB transceiver D – data output.
Reference output clock.
Remappable peripheral pin 5 input.
Remappable peripheral pin 5 output.
LATB<3> data output; not affected by analog input.
PORTB<3> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
A/D input channel 9.
CTMU edge 2 input.
Parallel Master Port address.
External USB transceiver D+ data output.
Remappable peripheral pin 6 input.
Remappable peripheral pin 6 output.
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