PIC18F26K20-E/SS Microchip Technology, PIC18F26K20-E/SS Datasheet - Page 262
![IC PIC MCU FLASH 32KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18F26K20-E/SS
Manufacturer Part Number
PIC18F26K20-E/SS
Description
IC PIC MCU FLASH 32KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
5.PIC18F26K20-EML.pdf
(430 pages)
Specifications of PIC18F26K20-E/SS
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1024Byte
Ram Memory Size
3.84375KB
Cpu Speed
64MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28SSOP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164307 - MODULE SKT FOR PM3 28SSOP
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F26K20-E/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F26K20-ISS PDF datasheet #3
- PIC18F26K20-ISS PDF datasheet #4
- PIC18F26K20-EML PDF datasheet #5
- Current page: 262 of 456
- Download datasheet (4Mb)
PIC18F2XK20/4XK20
18.4.2
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Clearing the
CSRC bit of the TXSTA register configures the device as
a slave. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
RX/DT and TX/CK pin output drivers must be disabled
by setting the corresponding TRIS bits.
18.4.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
TABLE 18-9:
DS41303G-page 262
INTCON
PIR1
PIE1
IPR1
RCSTA
TRISC
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1:
Name
are
Reserved in PIC18F2XK20 devices; always maintain these bits clear.
SYNCHRONOUS SLAVE MODE
EUSART Synchronous Slave
Transmit
EUSART Transmit Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
PSPIE
PSPIP
PSPIF
TRISC7
CSRC
SPEN
Bit 7
identical
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
(1)
(1)
(1)
TRISC6
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
(see
Section 18.4.1.3
TRISC5
DTRXP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
TRISC4
CKTXP
INT0IE
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
ADDEN
TRISC3
SENDB
BRG16
SSPIF
SSPIE
SSPIP
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
18.4.2.2
1.
2.
3.
4.
5.
6.
7.
8.
RBIE
Bit 3
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Set the RX/DT and TX/CK TRIS controls to ‘1’.
Clear the CREN and SREN bits.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
BRGH
FERR
transmission
Bit 2
—
Synchronous Slave Transmission
Set-up:
TMR2IE
TMR2IP
TMR2IF
TRISC1
INT0IF
OERR
TRMT
WUE
Bit 1
2010 Microchip Technology Inc.
by
writing
TMR1IF
TMR1IE
TMR1IP
TRISC0
ABDEN
RX9D
TX9D
RBIF
Bit 0
the
on page
Values
Reset
Least
59
62
62
62
61
62
61
61
61
61
61
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