PIC18F26K20-E/SS Microchip Technology, PIC18F26K20-E/SS Datasheet - Page 215
![IC PIC MCU FLASH 32KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18F26K20-E/SS
Manufacturer Part Number
PIC18F26K20-E/SS
Description
IC PIC MCU FLASH 32KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
5.PIC18F26K20-EML.pdf
(430 pages)
Specifications of PIC18F26K20-E/SS
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1024Byte
Ram Memory Size
3.84375KB
Cpu Speed
64MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28SSOP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164307 - MODULE SKT FOR PM3 28SSOP
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F26K20-E/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F26K20-ISS PDF datasheet #3
- PIC18F26K20-ISS PDF datasheet #4
- PIC18F26K20-EML PDF datasheet #5
- Current page: 215 of 456
- Download datasheet (4Mb)
17.4.4.5
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
FIGURE 17-12:
2010 Microchip Technology Inc.
WR
SSPCON1
SDA
SCL
CKP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Clock Synchronization and
the CKP bit
2
C bus have deasserted SCL. This
CLOCK SYNCHRONIZATION TIMING
2
C master device has
DX
Master device
asserts clock
PIC18F2XK20/4XK20
Master device
deasserts clock
DS41303G-page 215
DX – 1
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