PIC18LF14K22-I/P Microchip Technology, PIC18LF14K22-I/P Datasheet - Page 62
![IC PIC MCU FLASH 512KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF14K22-I/P
Manufacturer Part Number
PIC18LF14K22-I/P
Description
IC PIC MCU FLASH 512KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
4.PIC18LF14K22-IP.pdf
(382 pages)
Specifications of PIC18LF14K22-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
20-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, MSSP, SPI, USART
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18LF13K22-ISS PDF datasheet
- PIC18LF13K22-ISS PDF datasheet #2
- PIC18LF13K22-ISS PDF datasheet #3
- PIC18LF14K22-IP PDF datasheet #4
- Current page: 62 of 382
- Download datasheet (6Mb)
PIC18F1XK22/LF1XK22
5.6
Data EEPROM memory has its own code-protect bits in
Configuration
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 22.0
“Special Features of the CPU” for additional
information.
5.7
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during
parameter 33).
EXAMPLE 5-3:
TABLE 5-1:
DS41365C-page 62
EEADR
EEADRH
EECON1
EECON2
EEDATA
INTCON
IPR2
PIE2
PIR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Loop
Name
Operation During Code-Protect
Protection Against Spurious Write
the
CLRF
BCF
BCF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
BCF
BSF
EEPROM Control Register 2 (not a physical register)
EEPROM Data Register
GIE/GIEH
EEADR7
Power-up
OSCFIP
OSCFIE
OSCFIF
Words.
EEPGD
Bit 7
—
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
EEADR
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
LOOP
EECON1, WREN
INTCON, GIE
DATA EEPROM REFRESH ROUTINE
External
PEIE/GIEL
Timer
EEADR6
CFGS
Bit 6
C1IP
C1IE
C1IF
—
read
period
EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0
TMR0IE
Bit 5
C2IP
C2IE
C2IF
and
—
—
(T
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
; Disable writes
; Enable interrupts
PWRT
write
Preliminary
INT0IE
FREE
,
EEIP
EEIE
EEIF
Bit 4
—
WRERR
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
5.8
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM without exceeding the total number of write
cycles to a single byte. If this is the case, then an array
refresh must be performed. For this reason, variables
that change infrequently (such as constants, IDs,
calibration, etc.) should be stored in Flash program
memory.
RABIE
BCLIP
BCLIE
BCLIF
Bit 3
—
Using the Data EEPROM
TMR0IF
WREN
Bit 2
—
—
—
—
EEADR9 EEADR8
TMR3IP
TMR3IE
TMR3IF
INT0IF
© 2009 Microchip Technology Inc.
Bit 1
WR
RABIF
Bit 0
RD
—
—
—
on page
Values
Reset
253
253
253
253
253
251
254
254
254
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