PIC18LF14K22-I/P Microchip Technology, PIC18LF14K22-I/P Datasheet - Page 23
![IC PIC MCU FLASH 512KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF14K22-I/P
Manufacturer Part Number
PIC18LF14K22-I/P
Description
IC PIC MCU FLASH 512KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
4.PIC18LF14K22-IP.pdf
(382 pages)
Specifications of PIC18LF14K22-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
20-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, MSSP, SPI, USART
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18LF13K22-ISS PDF datasheet
- PIC18LF13K22-ISS PDF datasheet #2
- PIC18LF13K22-ISS PDF datasheet #3
- PIC18LF14K22-IP PDF datasheet #4
- Current page: 23 of 382
- Download datasheet (6Mb)
2.8
The Primary External Oscillator, when configured for
LP, XT or HS modes, incorporates an Oscillator Start-up
Timer (OST). The OST ensures that the oscillator starts
and provides a stable clock to the oscillator module.
The OST times out when 1024 oscillations on OSC1
have occurred. During the OST period, with the system
clock set to the Primary External Oscillator, the program
counter does not increment suspending program
execution. The OST period will occur following:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Wake-up from Sleep
• Oscillator being enabled
• Expiration of Power-up Timer (PWRT)
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Start-up
mode can be selected. See Section 2.11 “Two-Speed
Start-up Mode” for more information.
FIGURE 2-5:
© 2009 Microchip Technology Inc.
New Clk Ready
New Clk Ready
Low Speed
High Speed
System Clock
System Clock
IRCF <2:0>
Note 1: Start-up time includes T
IRCF <2:0>
New Clock
New Clock
Old Clock
Oscillator Start-up Timer
Old Clock
Select Old
High Speed
Low Speed
Select Old
CLOCK SWITCH TIMING
Start-up Time
Start-up Time
OST
(1024 T
(1)
Select New
Select New
(1)
OSC
) for external clocks, plus T
Preliminary
PIC18F1XK22/LF1XK22
Clock Sync
2.9
The device contains circuitry to prevent clock “glitches”
due to a change of the system clock source. To
accomplish this, a short pause in the system clock
occurs during the clock switch. If the new clock source
is not stable (e.g., OST is active), the device will
continue to execute from the old clock source until the
new clock source becomes stable. The timing of a
clock switch is as follows:
1.
2.
3.
4.
5.
6.
7.
Refer to Figure 2-5 for more details.
Clock Sync
SCS<1:0> bits of the OSCCON register are
modified.
The system clock will continue to operate from
the old clock until the new clock is ready.
Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
is ready.
The system clock is held low, starting at the next
falling edge of the old clock.
Clock switch circuitry waits for an additional two
rising edges of the new clock.
On the next falling edge of the new clock, the
low hold on the system clock is release and the
new clock is switched in as the system clock.
Clock switch is complete.
Clock Switching
PLL
(approx. 2 ms) for HSPLL mode.
Running
Running
DS41365C-page 23
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