PIC16F72-I/ML Microchip Technology, PIC16F72-I/ML Datasheet - Page 71
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PIC16F72-I/ML
Manufacturer Part Number
PIC16F72-I/ML
Description
IC PIC MCU FLASH 2KX14 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F72-ISO.pdf
(136 pages)
5.PIC16F72-ISO.pdf
(6 pages)
6.PIC16F72-ISO.pdf
(136 pages)
Specifications of PIC16F72-I/ML
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16F72-I/MLR
PIC16F72-I/MLR
PIC16F72-I/MLR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
11.11.1
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 11.14 for details on SLEEP
mode.
11.11.2
An overflow (FFh → 00h) in the TMR0 register will set
flag bit TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled
TMR0IE (INTCON<5>) (see Section 4.0).
EXAMPLE 11-1:
© 2007 Microchip Technology Inc.
MOVWF
SWAPF
CLRF
MOVWF
:
:(ISR)
:
SWAPF
MOVWF
SWAPF
SWAPF
on
INT INTERRUPT
TMR0 INTERRUPT
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
the
by
RB0/INT
SAVING STATUS, W AND PCLATH REGISTERS IN RAM
setting/clearing
pin,
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Insert user code here
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
flag
enable
bit
INTF
bit
11.11.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>) (see
Section 3.2).
11.12 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W, STATUS registers).
This will have to be implemented in software, as shown
in Example 11-1.
For the PIC16F72 device, the register W_TEMP must
be defined in both banks 0 and 1 and must be defined
at the same offset from the bank base address (i.e., if
W_TEMP is defined at 20h in bank 0, it must also be
defined at A0h in bank 1). The register STATUS_TEMP
is only defined in bank 0.
PORTB INTCON CHANGE
PIC16F72
DS39597C-page 69