PIC16F72-I/ML Microchip Technology, PIC16F72-I/ML Datasheet - Page 12

• Manufacturer Part Number: PIC16F72-I/ML
• Description: IC PIC MCU FLASH 2KX14 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F72-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16F72-I/MLR; PIC16F72-I/MLR

PIC16F72
TABLE 2-1:
DS39597C-page 10
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
Bank 1
(1)
(1)
(1)
(1)
(1,2)
(1)
1: These registers can be addressed from any bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
3: This bit always reads as a ‘1’.
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PCON
PR2
SSPADD
SSPSTAT
ADCON1
PIE1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
Name
—
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—
—
—
—
—
—
—
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—
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SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
Program Counter's (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTB Data Direction Register
PORTC Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
RBPU
Bit 7
SMP
IRP
GIE
—
—
—
—
—
INTEDG
PEIE
ADIE
Bit 6
CKE
RP1
—
—
—
—
PORTA Data Direction Register
TMR0IE
T0CS
Bit 5
RP0
D/A
—
—
—
—
2
C mode) Address Register
Write Buffer for the upper 5 bits of the PC
T0SE
Bit 4
INTE
TO
—
—
—
P
SSPIE
RBIE
Bit 3
PSA
PD
—
—
S
TMR0IF
CCP1IE
PCFG2
Bit 2
PS2
R/W
—
Z
TMR2IE
PCFG1
INTF
Bit 1
POR
PS1
DC
UA
© 2007 Microchip Technology Inc.
TMR1IE
PCFG0
RBIF
Bit 0
BOR
PS0
BF
C
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
1111 1111
1111 1111
---0 0000
0000 000x
-0-- 0000
---- --qq
1111 1111
0000 0000
0000 0000
---- -000
POR, BOR
Value on
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Details on
page:
43,48
19
13
18
12
19
21
23
25
18
14
15
17
41
44
54
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