PIC16F72-I/ML Microchip Technology, PIC16F72-I/ML Datasheet - Page 230
![IC PIC MCU FLASH 2KX14 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F72-I/ML
Manufacturer Part Number
PIC16F72-I/ML
Description
IC PIC MCU FLASH 2KX14 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F72-ISO.pdf
(136 pages)
5.PIC16F72-ISO.pdf
(6 pages)
6.PIC16F72-ISO.pdf
(136 pages)
Specifications of PIC16F72-I/ML
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16F72-I/MLR
PIC16F72-I/MLR
PIC16F72-I/MLR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F72-ISO PDF datasheet #4
- PIC16F72-ISO PDF datasheet #5
- PIC16F72-ISO PDF datasheet #6
- Current page: 230 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
15.3.4
DS31015A-page 15-10
SCK (CKP = 0,
SCK (CKP = 0,
SCK (CKP = 1,
SCK (CKP = 1,
SDO (CKE = 0)
SDO (CKE = 1)
SDI (SMP = 0)
Input
Sample (SMP = 0)
SDI (SMP = 1)
Input
Sample (SMP = 1)
Write to
SSPBUF
SSPIF
SSPSR to
SSPBUF
CKE = 1)
CKE = 0)
CKE = 0)
CKE = 1)
Master Operation
The master can initiate the data transfer at any time because it controls the SCK. The master
determines when the slave (Processor 2) is to broadcast data by the software protocol.
In master mode the data is transmitted/received as soon as the SSPBUF register is written to. If
the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed
clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately set). This could be useful in receiver appli-
cations as a “line activity monitor” mode.
The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then
would give waveforms for SPI communication as shown in
Figure 15-5
user programmable to be one of the following:
• F
• F
• F
• Timer2 output/2
This allows a maximum data rate of 5 Mbps (at 20 MHz).
Figure 15-3:
bit7
OSC
OSC
OSC
bit7
bit7
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit7
where the MSb is transmitted first. In master mode, the SPI clock rate (bit rate) is
CY
bit6
bit6
SPI Mode Waveform, Master Mode
)
CY
CY
)
)
bit5
bit5
bit4
bit4
bit3
bit3
bit2
bit2
bit1
bit1
Figure
1997 Microchip Technology Inc.
bit0
bit0
bit0
15-3,
bit0
Figure
Next Q4 cycle
after Q2
4 clock
modes
15-4, and
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