PIC12CE673-04/P Microchip Technology, PIC12CE673-04/P Datasheet - Page 599

• Manufacturer Part Number: PIC12CE673-04/P
• Description: IC MCU OTP 1KX14 A/D&EE 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE673-04/P

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Eeprom Size: 16 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 16Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 8
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Table 30-26:
Param.
D102
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
No.
1997 Microchip Technology Inc.
100
101
102
103
106
107
109
110
90
91
92
2: A fast-mode I
T
T
T
T
T
T
T
T
T
T
T
Cb
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
tsu;DAT
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output
the next data bit to the SDA line.
T
the SCL line is released.
Symbol
HIGH
LOW
R
F
SU
HD
HD
SU
SU
AA
BUF
R
max. + tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
:
:
:
:
:
STA
DAT
STO
STA
DAT
Example SSP I
250 ns must then be met. This will automatically be the case if the device does not stretch the
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall
time
START condition
setup time
START condition
hold time
Data input hold
time
Data input setup
time
STOP condition
setup time
Output valid from
clock
Bus free time
Bus capacitive loading
2
Section 30. Electrical Specifications
C-bus device can be used in a standard-mode I
2
Characteristic
C Bus Data Requirements
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
20 + 0.1Cb
20 + 0.1Cb
1.5T
1.5T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
2
C-bus system, but the requirement
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
2
C bus specification) before
PIC16CXXX must operate
at a minimum of 1.5 MHz
PIC16CXXX must operate
at a minimum of 10 MHz
PIC16CXXX must operate
at a minimum of 1.5 MHz
PIC16CXXX must operate
at a minimum of 10 MHz
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for repeated
START condition
After this period the first
clock pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission
can start
DS31030A-page 30-29
Conditions
30