PIC12CE673-04/P Microchip Technology, PIC12CE673-04/P Datasheet - Page 349

• Manufacturer Part Number: PIC12CE673-04/P
• Description: IC MCU OTP 1KX14 A/D&EE 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE673-04/P

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Eeprom Size: 16 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 16Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 8
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Connectivity: -
• Lead Free Status / Rohs Status: Details

18.4.3
18.4.3.1
1997 Microchip Technology Inc.
(RX/DT pin)
(RX/DT pin)
baud CLK
baud CLK
Sampling
Device Exceptions
x16 CLK
x16 CLK
RX
RX
The data on the RX/DT pin is sampled three times by a majority detect circuit to determine if a
high or a low level is present at the RX pin.
circuit. The sampling operates the same regardless of the state of the BRGH bit, only the source
of the x16 clock is different.
Figure 18-6:
All new devices will use the sampling scheme shown in
tion to the above sampling scheme are:
• PIC16C63
• PIC16C65
• PIC16C65A
• PIC16C73
• PIC16C73A
• PIC16C74
• PIC16C74A
These devices have a sampling circuitry that works as follows. If the BRGH bit (TXSTA<2>) is
clear (i.e., at the low baud rates), the sampling is done on the seventh, eighth and ninth falling
edges of a x16 clock
is done on the 3 clock edges preceding the second rising edge after the first falling edge of a x4
clock
Figure 18-7:
1
1
(Figure 18-8
2
2
3
3
4
4
RX Pin Sampling Scheme, BRGH = 0 or BRGH = 1
RX Pin Sampling Scheme (BRGH = 0)
and
(Figure
5
5
Figure
6
6
18-7). If bit BRGH is set (i.e., at the high baud rates), the sampling
18-9).
7
7
Samples
Samples
8
8
9
9
Start bit
Start bit
Figure 18-6
10
10
Section 18. USART
11
11
Baud CLK for all but start bit
Baud CLK for all but start bit
12
12
Figure
shows the waveform for the sampling
13
13
18-6. Devices that have an excep-
14
14
15
15
16
16
DS31018A-page 18-13
1
1
2
2
Bit0
Bit0
3
3
18