PIC12CE673-04/P Microchip Technology, PIC12CE673-04/P Datasheet - Page 74
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PIC12CE673-04/P
Manufacturer Part Number
PIC12CE673-04/P
Description
IC MCU OTP 1KX14 A/D&EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(3 pages)
4.PIC12CE673-10P.pdf
(14 pages)
5.PIC12CE673-10P.pdf
(12 pages)
Specifications of PIC12CE673-04/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
16Byte
Ram Memory Size
128Byte
Cpu Speed
4MHz
No. Of Timers
1
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE673-04/P
Manufacturer:
Microchip
Quantity:
486
PIC12C67X
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
CALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
DS30561B-page 74
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0
0
skip if (f<b>) = 1
None
If bit ’b’ in register ’f’ is ’1’, then the
next instruction is skipped.
If bit ’b’ is ’1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a 2 cycle instruction.
1
1(2)
Before Instruction
After Instruction
Call Subroutine
[ label ] CALL k
0
(PC)+ 1
k
(PCLATH<4:3>)
None
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two cycle instruction.
1
2
Before Instruction
After Instruction
HERE
FALSE
TRUE
HERE
01
10
f
b < 7
k
PC<10:0>,
127
2047
PC =
if FLAG<1> = 0,
PC =
if FLAG<1> = 1,
PC =
PC = Address HERE
PC = Address THERE
TOS = Address HERE+1
TOS,
11bb
BTFSS
GOTO
•
•
•
0kkk
CALL
THER
E
address HERE
address FALSE
address TRUE
FLAG,1
PROCESS_CO
DE
kkkk
PC<12:11>
bfff
kkkk
ffff
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
Clear f
[ label ] CLRF
0
00h
1
Z
The contents of register ’f’ are
cleared and the Z bit is set.
1
1
Before Instruction
After Instruction
Clear W
[ label ] CLRW
None
00h
1
Z
W register is cleared. Zero bit (Z)
is set.
1
1
Before Instruction
After Instruction
CLRF
CLRW
00
00
f
Z
Z
1999 Microchip Technology Inc.
127
(f)
(W)
FLAG_REG
FLAG_REG
Z
W
W
Z
0001
0001
FLAG_REG
=
=
=
f
0x5A
0x00
1
1fff
0000
=
=
=
0x5A
0x00
1
ffff
0011