ATTINY461-20MU Atmel, ATTINY461-20MU Datasheet - Page 86

• Manufacturer Part Number: ATTINY461-20MU
• Description: IC AVR MCU 4K 20MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY461-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire, SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.10.4
11.10.5
11.10.6
11.10.7
86
ATtiny261/461/861
TCNT0H – Timer/Counter0 Register High Byte
OCR0A – Timer/Counter0 Output Compare Register A
OCR0B – Timer/Counter0 Output Compare Register B
TIMSK – Timer/Counter0 Interrupt Mask Register
When 16-bit mode is selected (the TCW0 bit is set to one) the Timer/Counter Register TCNT0H
combined to the Timer/Counter Register TCNT0L gives direct access, both for read and write
operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes
are read and written simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by
all the other 16-bit registers. See
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0L). A match can be used to generate an Output Compare interrupt.
In 16-bit mode the OCR0A register contains the low byte of the 16-bit Output Compare Register.
To ensure that both the high and the low bytes are written simultaneously when the CPU writes
to these registers, the access is performed using an 8-bit temporary high byte register (TEMP).
This temporary register is shared by all the other 16-bit registers. See
16-bit Mode” on page
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0L in 8-bit mode and TCNTH in 16-bit mode). A match can be used to gen-
erate an Output Compare interrupt.
In 16-bit mode the OCR0B register contains the high byte of the 16-bit Output Compare Regis-
ter. To ensure that both the high and the low bytes are written simultaneously when the CPU
writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
isters in 16-bit Mode” on page
• Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
Bit
0x14 (0x34)
Read/Write
Initial Value
Bit
0x13 (0x33)
Read/Write
Initial Value
Bit
0x12 (0x32)
Read/Write
Initial Value
Bit
0x39 (0x59)
Read/Write
Initial Value
OCIE1D
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
80.
OCIE1A
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
80.
OCIE1B
“Accessing Registers in 16-bit Mode” on page 80
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
OCIE0A
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
TCNT0H[7:0]
OCR0A[7:0]
OCR0B[7:0]
OCIE0B
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
TOIE1
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
TOIE0
R/W
R/W
R/W
R/W
“Accessing Registers in
1
0
1
0
1
0
1
0
TICIE0
“Accessing Reg-
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
2588E–AVR–08/10
TCNT0H
OCR0A
OCR0B
TIMSK