PIC16F1937-I/P Microchip Technology, PIC16F1937-I/P Datasheet - Page 290
![IC PIC MCU FLASH 512KX14 40-PDIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16F1937-I/P
Manufacturer Part Number
PIC16F1937-I/P
Description
IC PIC MCU FLASH 512KX14 40-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(508 pages)
3.PIC16LF1933-ISS.pdf
(46 pages)
4.PIC16F1936-ISS.pdf
(2 pages)
5.PIC16F1936-ISS.pdf
(10 pages)
6.PIC16F1936-ISS.pdf
(40 pages)
7.PIC16F1936-ISS.pdf
(30 pages)
8.PIC16F1936-ISS.pdf
(12 pages)
9.PIC16LF1934-IML.pdf
(418 pages)
Specifications of PIC16F1937-I/P
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART/MI2C/SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
36
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
A/d Bit Size
10 bit
A/d Channels Available
14
Height
4.95 mm
Length
53.21 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
14.73 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1937-I/PT
Manufacturer:
CYPRESS
Quantity:
460
Company:
Part Number:
PIC16F1937-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC16F1937-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1933-ISS PDF datasheet #3
- PIC16F1936-ISS PDF datasheet #4
- PIC16F1936-ISS PDF datasheet #5
- PIC16F1936-ISS PDF datasheet #6
- PIC16F1936-ISS PDF datasheet #7
- PIC16F1936-ISS PDF datasheet #8
- PIC16LF1934-IML PDF datasheet #9
- Current page: 290 of 418
- Download datasheet (7Mb)
PIC16F193X/LF193X
22.4.4
The I
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 22-8 shows wave
forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I
states no bus collision can occur on a Start.
22.4.5
A Stop condition is a transition of the SDA line from
low to high state while the SCL line is high.
FIGURE 22-9:
DS41364A-page 288
Note: The Philips I
Note: At least one SCL low time must appear
2
C specification defines a Start condition as a
START CONDITION
STOP CONDITION
bus collision cannot occur on a Start, and
should occur during the address sequence.
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
SDA
SCL
I
2
2
C Specification states that a
C START AND STOP CONDITIONS
Condition
Start
S
2
C Specification that
Data Allowed
Change of
Preliminary
22.4.6
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully address, matching
both high and low address bytes, the master can issue
a Restart and the high address byte with the R/W bit
set. The slave logic will then hold the clock and pre-
pare to clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop condi-
tion, a high address with R/W clear, or high address
match fails.
22.4.7
The SCIE and PCIE bits of the SSPCON3 register can
enable the generation of an interrupt in Slave mode.
Slave modes where interrupt on Start and Stop detect
are already enabled, these bits will have no effect.
Data Allowed
RESTART CONDITION
START/STOP CONDITION INTERRUPT
MASKING
Change of
© 2008 Microchip Technology Inc.
Condition
Stop
P
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