PIC16F1937-I/P Microchip Technology, PIC16F1937-I/P Datasheet - Page 183

• Manufacturer Part Number: PIC16F1937-I/P
• Description: IC PIC MCU FLASH 512KX14 40-PDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-I/P

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/MI2C/SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 14
• Height: 4.95 mm
• Length: 53.21 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 14.73 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 18-2:
TABLE 18-2:
© 2008 Microchip Technology Inc.
ANSELA
ANSELB
ANSELD
INTCON
OPTION_REG
PIE1
PIR1
T1CON
TxCON
TRISA
TRISB
TRISD
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the capacitive
bit 7
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-0
Note 1:
Name
U-0
—
2:
sensing module.
These channels are not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938.
This bit is not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, read as ‘0’
TMR1CS1 TMR1CS0
TMR1GIE
TMR1GIF
WPUEN
Unimplemented: Read as ‘0’
CPSCH<3:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
If CPSON = 1:
TRISD7
TRISA7
TRISB7
ANSD7
SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Bit 7
GIE
—
—
—
These bits are ignored. No channel is selected.
U-0
0000 = channel 0, (CPS0)
0001 = channel 1, (CPS1)
0010 = channel 2, (CPS2)
0011 = channel 3, (CPS3)
0100 = channel 4, (CPS4)
0101 = channel 5, (CPS5)
0110 = channel 6, (CPS6)
0111 = channel 7, (CPS7)
1000 = channel 8, (CPS8
1001 = channel 9, (CPS9
1010 = channel 10, (CPS10
1011 = channel 11, (CPS11
1100 = channel 12, (CPS12
1101 = channel 13, (CPS13
1110 = channel 14, (CPS14
1111 = channel 15, (CPS15
—
CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
TOUTPS3
INTEDG
TRISD6
TRISA6
TRISB6
ANSD6
ADIE
Bit 6
PEIE
ADIF
—
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
TOUTPS2
T1CKPS1
TMR0CS
TMR0IE
TRISA5
TRISB5
TRISD5
ANSA5
ANSB5
ANSD5
RCIE
RCIF
Bit 5
R/W-0/0
(1)
(1)
CPSCH4
)
)
(1)
(1)
(1)
(1)
(1)
(1)
TOUTPS1
T1CKPS0
TMR0SE
Preliminary
TRISA4
TRISB4
TRISD4
ANSA4
ANSB4
ANSD4
)
)
)
)
)
)
Bit 4
INTE
TXIE
TXIF
(1, 2)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
T1OSCEN
TOUTPS0
CPSCH3
TRISA3
TRISB3
TRISD3
ANSD3
ANSA3
ANSB3
SSPIE
SSPIF
IOCIE
Bit 3
PSA
PIC16F193X/LF193X
(1)
TMRXON
T1SYNC
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISB2
TRISD2
ANSD2
ANSA2
ANSB2
Bit 2
PS2
CPSCH2
R/W-0/0
TXCKPS1
TMR2IE
TMR2IF
TRISA1
TRISB1
TRISD1
ANSD1
ANSA1
ANSB1
Bit 1
INTF
PS1
—
CPSCH1
R/W-0/0
TXCKPS0
TMR1ON
TMR1IE
TMR1IF
TRISA0
TRISB0
TRISD0
ANSD0
ANSA0
ANSB0
IOCIF
Bit 0
PS0
DS41364A-page 181
CPSCH0
R/W-0/0
Register
on Page
169
175
86
91
97
73
51
74
77
86
91
97
bit 0