PIC18F24J11-I/SO Microchip Technology, PIC18F24J11-I/SO Datasheet - Page 92

• Manufacturer Part Number: PIC18F24J11-I/SO
• Description: IC PIC MCU FLASH 16K 2V 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24J11-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILAC164332 - MODULE SKT FOR 28SOIC 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F46J11 FAMILY
5.4.3.2
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
• POSTINC: accesses the FSR value, then
• PREINC: increments the FSR value by ‘1’, then
• PLUSW: adds the signed value of the W register
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
5.4.3.3
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1, using INDF0 as an operand, will
return 00h. Attempts to write to INDF1, using INDF0 as
the operand, will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to
FSR2H:FSR2L.
DS39932C-page 92
automatically decrements it by ‘1’ thereafter
automatically increments it by ‘1’ thereafter
uses it in the operation
(range of 127 to 128) to that of the FSR and uses
the new value in the operation
FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
Operations by FSRs on FSRs
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
Similarly, operations by Indirect Addressing are gener-
ally permitted on all other SFRs. Users should exercise
appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
5.5
The operation of program memory is unaffected by the
use of the extended instruction set.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 5.2.4 “Two-Word Instructions”.
5.6
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core PIC18
instructions is different. This is due to the introduction of
a new addressing mode for the data memory space.
This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
Program Memory and the
Extended Instruction Set
Data Memory and the Extended
Instruction Set
© 2009 Microchip Technology Inc.