ATTINY88-AU Atmel, ATTINY88-AU Datasheet - Page 37
![MCU AVR 8K ISP FLASH 1.8V 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATTINY88-AU
Manufacturer Part Number
ATTINY88-AU
Description
MCU AVR 8K ISP FLASH 1.8V 32TQFP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY88-AU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire/I2S/SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
28
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATQT600, ATAVRTS2080B
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY88-AU
Manufacturer:
ATMEL
Quantity:
5 000
Company:
Part Number:
ATTINY88-AU
Manufacturer:
ATMEL
Quantity:
3 000
Part Number:
ATTINY88-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
7.1.2
7.1.3
7.2
8008G–AVR–04/11
Software BOD Disable
ADC Noise Reduction Mode
Power-Down Mode
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the SPI interrupts. If wake-up from the Analog Comparator interrupt is not required, the
Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator
Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the
ADC is enabled, a conversion starts automatically when this mode is entered.
When the SM[1:0] bits are written to 01, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-
wire Serial Interface address watch and the Watchdog to continue operating (if enabled). This
sleep mode basically halts clk
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a
Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, an EEPROM
ready interrupt, an external level interrupt on INT0 or INT1 or a pin change interrupt can wake up
the MCU from ADC Noise Reduction mode.
When the SM[1:0] bits are written to 10, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the external oscillator is stopped, while the external interrupts, the 2-
wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an
External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, a 2-wire
Serial Interface address match, an external level interrupt on INT0 or INT1, or a pin change
interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing
operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
Reset Time-out period, as described in
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see
189), the BOD is actively monitoring the power supply voltage during a sleep period. To save
power, it is possible for software to disable the BOD in Power-down mode. The sleep mode
power consumption will then be at the same level as when BOD is globally disabled by fuses. If
disabled by software, the BOD is turned off immediately after entering the sleep mode and auto-
matically turned on upon wake-up. This ensures safe operation in case the V
dropped during the sleep period.
When the BOD has been disabled the wake-up time from sleep mode will be the same as the
wake-up time from RESET. This is in order to ensure the BOD is working correctly before the
MCU continues executing code.
BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see
“MCUCR – MCU Control Register” on page
I/O
, clk
CPU
, and clk
“Clock Sources” on page
40. Writing this bit to one turns off the BOD in
FLASH
, while allowing the other clocks to run.
“External Interrupts” on page 53
29.
ATtiny48/88
Table 20-4 on page
CC
level has
37