ATTINY88-AU Atmel, ATTINY88-AU Datasheet - Page 215

• Manufacturer Part Number: ATTINY88-AU
• Description: MCU AVR 8K ISP FLASH 1.8V 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY88-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire/I2S/SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATQT600, ATAVRTS2080B
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.10 Parallel Programming Characteristics
Figure 22-6. Parallel Programming Timing, Including some General Timing Requirements
Figure 22-7. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
8008G–AVR–04/11
(DATA, XA0/1, BS1, BS2)
PAGEL
DATA
CLKI
BS1
XA0
XA1
1. The timing requirements shown in
Data & Contol
RDY/BSY
PAGEL
ADDR0 (Low Byte)
LOAD ADDRESS
CLKI
(LOW BYTE)
WR
t
t
BVPH
DVXH
Figure 22-6
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
t
t
XHXL
PHPL
(i.e., t
z
DVXH
t
t
t
t
t
XLDX
PLBX
XLXH
XLWL
PLWL
, t
XHXL
, and t
t
(HIGH BYTE)
BVWL
LOAD DATA
XLDX
DATA (High Byte)
) also apply to loading operation.
t
t
WLWH
XLPH
WLRL
LOAD DATA
(1)
t
PLXH
t
WLBX
ATtiny48/88
LOAD ADDRESS
(LOW BYTE)
ADDR1 (Low Byte)
t
WLRH
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