PIC18F44K20-I/ML Microchip Technology, PIC18F44K20-I/ML Datasheet - Page 353
![IC PIC MCU FLASH 8KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F44K20-I/ML
Manufacturer Part Number
PIC18F44K20-I/ML
Description
IC PIC MCU FLASH 8KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F44K20-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F25K20T-ISS PDF datasheet #3
- PIC18F25K20T-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 353 of 430
- Download datasheet (7Mb)
TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2008 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If CNT
PC
If CNT
PC
Q1
Q1
Q1
No
No
No
register ‘f’
operation
operation
operation
Test f, skip if 0
TSTFSZ f {,a}
0 ≤ f ≤ 255
a ∈ [0,1]
skip if f = 0
None
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
Q2
Q2
No
Q2
No
No
=
=
=
≠
=
by a 2-word instruction.
Address (HERE)
00h,
Address (ZERO)
00h,
Address (NZERO)
TSTFSZ
:
:
011a
operation
operation
operation
Process
Data
Q3
Q3
No
Q3
No
No
CNT, 1
ffff
operation
operation
operation
operation
Q4
Q4
Q4
No
No
No
No
ffff
Preliminary
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
PIC18F2XK20/4XK20
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
literal ‘k’
Exclusive OR literal with W
XORLW k
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
1
1
XORLW
Read
Q2
0000
B5h
1Ah
0AFh
1010
Process
Data
Q3
DS41303D-page 351
kkkk
Write to W
Q4
kkkk
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