PIC18F44K20-I/ML Microchip Technology, PIC18F44K20-I/ML Datasheet - Page 264
![IC PIC MCU FLASH 8KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F44K20-I/ML
Manufacturer Part Number
PIC18F44K20-I/ML
Description
IC PIC MCU FLASH 8KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F44K20-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F25K20T-ISS PDF datasheet #3
- PIC18F25K20T-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 264 of 430
- Download datasheet (7Mb)
PIC18F2XK20/4XK20
19.1
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Results formatting
19.1.1
The ANSEL, ANSELH, TRISA, TRISB and TRISE reg-
isters all configure the A/D port pins. Any port pin
needed as an analog input should have its correspond-
ing ANSx bit set to disable the digital input buffer and
TRISx bit set to disable the digital output driver. If the
TRISx bit is cleared, the digital output level (V
V
The A/D operation is independent of the state of the
ANSx bits and the TRIS bits.
19.1.2
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 19.2
“ADC Operation” for more information.
19.1.3
The VCFG bits of the ADCON1 register provide
independent control of the positive and negative
voltage references. The positive voltage reference can
be either V
the negative voltage reference can be either V
external voltage source.
DS41303D-page 262
OL
Note 1: When reading the PORT register, all pins
) will be converted.
2: Analog levels on any pin with the corre-
3: The
ADC Configuration
DD
PORT CONFIGURATION
CHANNEL SELECTION
ADC V
with their corresponding ANSx bit set
read as cleared (a low level). However,
analog conversion of pins configured as
digital inputs (ANSx bit cleared and
TRISx
converted.
sponding ANSx bit cleared may cause the
digital input buffer to consume current out
of the device’s specification limits.
Register 3H configures PORTB pins to
reset as analog or digital pins by
controlling how the bits in ANSELH are
reset.
or an external voltage source. Likewise,
PBADEN
OLTAGE REFERENCE
bit
set)
bit
will
in
be
Configuration
accurately
SS
OH
or an
Preliminary
or
19.1.4
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Acquisition time is set with the ACQT<2:0> bits of the
ADCON2 register. Acquisition delays cover a range of
2 to 20 T
module continues to sample the input for the selected
acquisition time, then automatically begins a conver-
sion. Since the acquisition time is programmed, there is
no need to wait for an acquisition time between select-
ing a channel and setting the GO/DONE bit.
Manual
ACQT<2:0> = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT<2:0> bits and
is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. When an acquisition time is programmed, there
is no indication of when the acquisition time ends and
the conversion begins.
19.1.5
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON2 register. There
are seven possible clock options:
• F
• F
• F
• F
• F
• F
• F
The time to complete one bit conversion is defined as
T
as shown in Figure 19-3.
For correct conversion, the appropriate T
must be met. See A/D conversion requirements in
Table 26-25 for more information. Table 19-1 gives
examples of appropriate ADC clock selections.
AD
Note:
OSC
OSC
OSC
OSC
OSC
OSC
RC
. One full 10-bit conversion requires 11 T
(dedicated internal oscillator)
/2
/4
/8
/16
/32
/64
AD
SELECTING AND CONFIGURING
ACQUISITION TIME
. When the GO/DONE bit is set, the A/D
Unless using the F
system clock frequency will change the
ADC
adversely affect the ADC result.
acquisition
CONVERSION CLOCK
clock
© 2008 Microchip Technology Inc.
frequency,
is
RC
, any changes in the
selected
AD
which
specification
AD
periods
when
may
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