PIC18F44K20-I/ML Microchip Technology, PIC18F44K20-I/ML Datasheet - Page 28
![IC PIC MCU FLASH 8KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F44K20-I/ML
Manufacturer Part Number
PIC18F44K20-I/ML
Description
IC PIC MCU FLASH 8KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F44K20-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F25K20T-ISS PDF datasheet #3
- PIC18F25K20T-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 28 of 430
- Download datasheet (7Mb)
PIC18F2XK20/4XK20
2.2
The OSCCON register (Register 2-1) controls several
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.
• Main System Clock Selection (SCS)
• Internal Frequency selection bits (IRCF)
• Clock Status bits (OSTS, IOFS)
• Power management selection (IDLEN)
2.2.1
The System Clock Select bits, SCS<1:0>, select the
main clock source. The available clock sources are
• Primary clock defined by the FOSC<3:0> bits of
• Secondary clock (Timer1 oscillator)
• Internal oscillator block (HFINTOSC and
The clock source changes immediately after one or
more of the bits is written to, following a brief clock tran-
sition interval. The SCS bits are cleared to select the
primary clock on all forms of Reset.
2.2.2
The
(IRCF<2:0>) select the frequency output of the internal
oscillator block. The choices are the LFINTOSC source
(31 kHz), the HFINTOSC source (16 MHz) or one of
the frequencies derived from the HFINTOSC post-
scaler (31.25 kHz to 8 MHz). If the internal oscillator
block is supplying the main clock, changing the states
of these bits will have an immediate change on the
internal oscillator’s output. On device Resets, the out-
put frequency of the internal oscillator is set to the
default frequency of 1 MHz.
2.2.3
When a nominal output frequency of 31 kHz is selected
(IRCF<2:0> = 000), users may choose which internal
oscillator acts as the source. This is done with the
INTSRC bit of the OSCTUNE register. Setting this bit
selects the HFINTOSC as a 31.25 kHz clock source by
enabling the divide-by-512 output of the HFINTOSC
postscaler. Clearing INTSRC selects LFINTOSC (nom-
inally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise HFINTOSC as a clock source, while maintain-
ing power savings with a very low clock speed. Regard-
less of the setting of INTSRC, LFINTOSC always
remains the clock source for features such as the
Watchdog Timer and the Fail-Safe Clock Monitor.
DS41303D-page 26
CONFIG1H. The primary clock can be the primary
oscillator, an external clock, or the internal oscilla-
tor block.
LFINTOSC).
Internal
Oscillator Control
MAIN SYSTEM CLOCK SELECTION
INTERNAL FREQUENCY
SELECTION
LOW FREQUENCY SELECTION
Oscillator
Frequency
Select
Preliminary
bits
2.2.4
The OSTS and IOFS bits of the OSCCON register, and
the T1RUN bit of the T1CON register, indicate which
clock source is currently providing the main clock. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
device clock. The IOFS bit indicates when the internal
oscillator block has stabilized and is providing the
device clock in HFINTOSC Clock modes. The IOFS
and OSTS Status bits will both be set when
SCS<1:0> = 00 and HFINTOSC is the primary clock.
The T1RUN bit indicates when the Timer1 oscillator is
providing the device clock in secondary clock modes.
When SCS<1:0> ≠ 00, only one of these three bits will
be set at any time. If none of these bits are set, the
LFINTOSC is providing the clock or the HFINTOSC has
just started and is not yet stable.
2.2.5
The IDLEN bit of the OSCCON register determines if
the device goes into Sleep mode or one of the Idle
modes when the SLEEP instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
2: It is recommended that the Timer1
CLOCK STATUS
POWER MANAGEMENT
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit of the T1CON register. If
the Timer1 oscillator is not enabled, then
the main oscillator will continue to run
from the previously selected source. The
source will then switch to the secondary
oscillator after the T1OSCEN bit is set.
oscillator be operating and stable before
selecting the secondary clock source or a
very long delay may occur while the
Timer1 oscillator starts.
© 2008 Microchip Technology Inc.
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