PIC16F1937-I/ML Microchip Technology, PIC16F1937-I/ML Datasheet - Page 9

• Manufacturer Part Number: PIC16F1937-I/ML
• Description: IC PIC MCU FLASH 512KX14 44-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-I/ML

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC16F
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In the new view, the 80-byte blocks of GPR memory are
stacked without the common memory or the SFRs to
separate them. This allows a 90-byte data structure to
span two banks of memory without concern for
overwriting unrelated memory locations. To use this
view of GPR memory, simply point an FSR at a location
after 0x2000.
PROGRAM MEMORY READ VIA FSR
Another useful feature of the indirect addressing
system is access to the low 8-bits of the program
memory.
Access to the program memory starts at FSR address
0x8000. The following code example shows how to
access a memory table with the FSR.
EXAMPLE 3:
The compiler knows when a label references a
program memory address. If a program memory
address is the target of the high directive, the high
directive will return the high part of the address with the
MSB set. This will assure that the FSR address is a
proper address for accessing the program memory.
When accessing program memory with the FSR, each
read of the INDF register will take 2 cycles. The second
cycle is needed to fetch the data.
Banking and Paging
Banking and paging have always been a complication
of PIC12/16 microcontrollers. To further enhance the
new PIC12/16, new instructions were added to simplify
paging and banking. These new instructions also allow
the number of pages and banks to increase to 32 banks
and 16 pages.
BANKING INSTRUCTION
Increasing the number of banks to 32 was impossible
with the RP0, RP1 bits in the STATUS register. These
bits were removed and replaced with a BSR register.
Along with BSR, a new instruction was added to load
© 2009 Microchip Technology Inc.
Code
table_label
.. More Table Data ...
MOVLW high table_label
MOVWF FSR0H
MOVLW low table_label
MOVWF FSR0L
MOVF
...
Lots More Code
...
MOVLW 0xAA
MOVLW 0xAB
FSR0,W
the BSR from a literal. The MOVLB instruction does in
one cycle what the BANKSEL macro currently does in
one or two instructions depending upon the device
memory size. By making banking one instruction, the
penalty for banking was reduced by up to 50%.
PAGING INSTRUCTION
The need for paging is due to the CALL and GOTO
instructions. These two instructions can reach any
address inside of a 2K word window. To leave this
window, the PCLATH must be updated before the call
or GOTO can take place. To increase the efficiency of
editing PCLATH, a new instruction, MOVLP, has been
added. MOVLP is the instruction equivalent of the
PAGESEL macro. In the enhanced PIC12/16, every
CALL or GOTO could be preceded by a MOVLP for a 2-
word, 3-cycle operation that can reach the entire
program memory.
MATH
Arithmetic on the PIC12/16 has always been very easy
but multi-byte operations could be made easier by add-
ing support for carry and arithmetic shifts.
ARITHMETIC WITH CARRY
Add and subtract have been extended to support carry
or borrow. Only adds and subtracts with file registers
are supported with the Carry or Borrow. The new
instructions work exactly as the legacy instructions
except the Carry/Borrow flag is included in the opera-
tion. The original add and subtract instructions are still
present in the enhanced PIC12/16. All existing algo-
rithms will work unchanged but a speed-up is possible
by selectively replacing some instruction sequences
with the new instructions.
SHIFTS INSTEAD OF ROTATES
The legacy PIC12/16 has a pair of 9-bit rotate instruc-
tions. These instructions rotate through the Carry flag
so 9 rotates will result in the original value. In addition
to the rotates, the new PIC12/16 has 3 shift instruc-
tions.
1.
2.
3.
4.
ASRF – Arithmetic Right Shift
LSRF – Logical Right Shift
LSLF – Logical Left Shift
ASLF – Arithmetic Left Shift is assembled as
LSLF
DS41375A-page 9