PIC16F1937-I/ML Microchip Technology, PIC16F1937-I/ML Datasheet - Page 2

IC PIC MCU FLASH 512KX14 44-QFN

PIC16F1937-I/ML

Manufacturer Part Number
PIC16F1937-I/ML
Description
IC PIC MCU FLASH 512KX14 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr

Specifications of PIC16F1937-I/ML

Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC16F
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
32MHz
No. Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
TABLE 1:
The core registers in the enhanced PIC12/16 are the
same as the legacy registers with the addition of a
second FSR/INDF, the BSR and mapping the W
register in WREG. The IRP, RP0 and RP1 bits are no
longer present in the STATUS because the BSR is now
available and the FSRs are now 16 bits wide.
TABLE 2:
These instructions were designed to fit inside the
“holes” in the existing 14-bit instruction word. By fitting
the existing memory design, the cost of the enhanced
devices was kept similar to the existing PIC12/16,
simplifying the decision to use the new features.
DS41375A-page 2
Note 1: All cycle counts increase by 1 if the file address points to INDF (0 or 1) and FSR points to program
Address
LSLF/ASRF
Mnemonic
0x0A
0x0B
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
ADDFSR
ADDWFC
SUBWFB
CALLW
MOVLB
MOVLP
MOVIW
MOVWI
RESET
ASRF
LSRF
BRA
BRW
memory.
SFR ADDRESSES
NEW INSTRUCTIONS
Operands
Register
PCLATH
INTCON
STATUS
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
BSR
PCL
f,d
f,d
f,d
f,d
f,d
k
k
k
k
*
*
-
-
-
Subtract W from F with Borrow
Move Literal to PCLATH
Add W and F with Carry
Branch Relative with W
Arithmetic Shift Right
Call Absolute with W
Move Literal to BSR
Add literal to FSRn
Logical Shift Right
Move INDFn to W
Move W to INDFn
Logical Shift Left
Branch Relative
Description
CPU Reset
Indirect Address for INDF0, High Byte
Indirect Address for INDF1, High Byte
Indirect Address for INDF0, Low Byte
Indirect Address for INDF1, Low Byte
Program Counter High Byte Latch
New Instructions
The new instructions improve arithmetic, simplify
paging and banking, and extend the capabilities of the
indirect addressing modes.
Interrupt Control Register
Indirect File Register 0
Indirect File Register 1
Program Counter Low
Bank Select Register
ALU Status Register
Description
W Register
© 2009 Microchip Technology Inc.
Cycles
1
1
1
1
2
2
2
1
1
1
1
1
1
1
(1)
Affected
C,DC,Z
C,DC,Z
C,DC,Z
Status
C
C
C
Z

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