ATTINY2313-20MU Atmel, ATTINY2313-20MU Datasheet - Page 57
ATTINY2313-20MU
Manufacturer Part Number
ATTINY2313-20MU
Description
IC MCU AVR 2K FLASH 20MLF
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY2313-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI/UART/USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Package
20MLF EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q2312268A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY2313-20MU
Manufacturer:
原装ATMEL
Quantity:
20 000
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2543L–AVR–08/10
Table 29
Figure 25 on page
Table 29. Overriding Signals for Alternate Functions PD7..PD4
Table 30. Overriding Signals for Alternate Functions in PD3..PD0
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
and
PD6/ICP
0
0
0
0
0
0
0
ICP ENABLE
1
ICP INPUT
–
PD3/INT1
0
0
0
0
0
0
0
INT1 ENABLE
1
INT1 INPUT
–
Table 30
51.
relates the alternate functions of Port D to the overriding signals shown in
PD2/INT0/XCK/
CKOUT
0
0
0
0
XCKO_PVOE
XCKO_PVOV
0
INT0 ENABLE/
XCK INPUT
ENABLE
1
INT0 INPUT/
XCK INPUT
–
PD5/OC1B/T1
0
0
0
0
OC1B_PVOE
OC1B_PVOV
0
T1 ENABLE
1
T1 INPUT
–
PD1/TXD
TXD_OE
0
TXD_OE
1
TXD_OE
TXD_PVOV
0
0
0
–
–
PD4/T0
0
0
0
0
0
0
0
T0 ENABLE
1
T0 INPUT
AIN1
PD0/RXD
RXD_OE
PORTD0 • PUD
RXD_EN
0
0
0
0
0
0
RXD INPUT
–
57
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