PIC18F13K22-I/SO Microchip Technology, PIC18F13K22-I/SO Datasheet - Page 208

• Manufacturer Part Number: PIC18F13K22-I/SO
• Description: IC MCU 8BIT 8KB FLASH 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K22-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 20SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Height: 2.05 mm
• Length: 12.8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V, 2.7 V
• Width: 7.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
16.1
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Results formatting
16.1.1
The ANSEL, ANSELH, TRISA, TRISB and TRISE reg-
isters all configure the A/D port pins. Any port pin
needed as an analog input should have its correspond-
ing ANSx bit set to disable the digital input buffer and
TRISx bit set to disable the digital output driver. If the
TRISx bit is cleared, the digital output level (V
V
The A/D operation is independent of the state of the
ANSx bits and the TRIS bits.
16.1.2
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 16.2
“ADC Operation” for more information.
16.1.3
The PVCFG and NVCFG bits of the ADCON1 register
provide independent control of the positive and
negative voltage references, respectively. The positive
voltage reference can be either V
external voltage
reference can be either V
source.
DS41365D-page 208
OL
Note 1: When reading the PORT register, all pins
) will be converted.
2: Analog levels on any pin with the corre-
ADC Configuration
PORT CONFIGURATION
CHANNEL SELECTION
ADC V
with their corresponding ANSx bit set
read as cleared (a low level). However,
analog conversion of pins configured as
digital inputs (ANSx bit cleared and
TRISx
converted.
sponding ANSx bit cleared may cause the
digital input buffer to consume current out
of the device’s specification limits.
OLTAGE REFERENCE
source.
bit
set)
SS
The negative voltage
or an external voltage
will
DD
be
, FVR or an
accurately
OH
Preliminary
or
16.1.4
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Acquisition time is set with the ACQT<2:0> bits of the
ADCON2 register. Acquisition delays cover a range of
2 to 20 T
module continues to sample the input for the selected
acquisition time, then automatically begins a conver-
sion. Since the acquisition time is programmed, there is
no need to wait for an acquisition time between select-
ing a channel and setting the GO/DONE bit.
Manual
ACQT<2:0> = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT<2:0> bits and
is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. When an acquisition time is programmed, there
is no indication of when the acquisition time ends and
the conversion begins.
16.1.5
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON2 register. There
are seven possible clock options:
• F
• F
• F
• F
• F
• F
• F
The time to complete one bit conversion is defined as
T
as shown in Figure 16-3.
For correct conversion, the appropriate T
must be met. See A/D conversion requirements in
Table 25-9 for more information. Table 16-1 gives
examples of appropriate ADC clock selections.
AD
Note:
OSC
OSC
OSC
OSC
OSC
OSC
RC
. One full 10-bit conversion requires 11 T
(dedicated internal oscillator)
/2
/4
/8
/16
/32
/64
AD
SELECTING AND CONFIGURING
ACQUISITION TIME
. When the GO/DONE bit is set, the A/D
Unless using the F
system clock frequency will change the
ADC
adversely affect the ADC result.
acquisition
CONVERSION CLOCK
clock
 2010 Microchip Technology Inc.
frequency,
is
RC
, any changes in the
selected
AD
which
specification
AD
periods
when
may