PIC18F13K50-I/SS Microchip Technology, PIC18F13K50-I/SS Datasheet - Page 6

• Manufacturer Part Number: PIC18F13K50-I/SS
• Description: IC PIC MCU FLASH 8KB 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F1XK50/PIC18LF1XK50
3.0
For the PIC18F14K50/PIC18LF14K50 device, the
program Flash space extends from 0000h to 03FFFh
(16 Kbytes)
PIC18F13K50/PIC18LF13K50 device, the program
Flash space extends from 0000h to 01FFFh (8 Kbytes)
in two 4-Kbyte blocks.
For the PIC18F14K50/PIC18LF14K50 addresses
0000h through 0FFFh, however, define a “Boot Block”
region that is treated separately from Block 0. For the
PIC18F13K50/PIC18LF13K50
through 07FFh, define the “Boot Block” region. All of
these blocks define code protection boundaries within
the program Flash space. The size of the Boot Block in
the PIC18F14K50/PIC18LF14K50 devices can be
configured as 2K, or 4 Kbyte (see Figure 3-1). The size
FIGURE 3-1:
DS41342E-page 6
MEMORY MAPS
Note 1: Boot Block size is determined by the BBSIZ bit in the CONFIG4L register.
in
00FFFFh
100000h
1FFFFFh
two
000000h
MEMORY MAP AND THE PROGRAM FLASH SPACE FOR PIC18F14K50/
PIC18LF14K50 DEVICES
8-Kbyte
Unimplemented
Program Flash
Configuration
Read as ‘0’
and ID
Space
addresses
blocks.
Advance Information
For
0000h
the
Unimplemented
Boot Block*
BBSIZ = 1
Read ‘0’s
Block 0
Block 1
MEMORY SIZE/DEVICE
(PIC18F14K50)
of the Boot Block in the PIC18F13K50/PIC18LF13K50
devices can be configured as 1K, or 2 Kbytes, as
illustrated in Figure 3-1. This is done through the
BBSIZ bit in the Configuration register, CONFIG4L. It is
important to note that increasing the size of the Boot
Block decreases the size of the Block 0.
TABLE 3-1:
PIC18LF13K50
PIC18LF14K50
8 KW
PIC18F13K50/
PIC18F14K50/
Unimplemented
Device
Boot Block
BBSIZ = 0
Read ‘0’s
Block 0
Block 1
(1)
IMPLEMENTATION OF
PROGRAM FLASH
Program Flash Size (Words)
 2010 Microchip Technology Inc.
0003FFh
0007FFh
000FFFh
001FFFh
00FFFFh
000000h
000400h
000800h
001000h
002000h
Address
Range
000000h-000FFFh (4K)
000000h-001FFFh (8K)