PIC18F13K50-I/SS Microchip Technology, PIC18F13K50-I/SS Datasheet - Page 13

• Manufacturer Part Number: PIC18F13K50-I/SS
• Description: IC PIC MCU FLASH 8KB 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 4-2:
4.1.2
When using low-voltage ICSP, the part must be
supplied by the voltage specified in parameter D111 if
a Bulk Erase is to be executed. All other Bulk Erase
details, as described above, apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 4.1.3 “ICSP Row Erase” and Section 4.2.1
“Modifying Program Flash”.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the Bulk Erase
limit, follow the methodology described in Section 4.3
“Data EEPROM Programming” and write ‘1’s to the
array.
 2010 Microchip Technology Inc.
PGC
PGD
4-bit Command
1
0
LOW-VOLTAGE ICSP BULK ERASE
2
0
3
1
4
1
P5
BULK ERASE TIMING DIAGRAM
1
1
Data Payload
2
1
16-bit
15 16
0
0
P5A
PIC18F1XK50/PIC18LF1XK50
4-bit Command
1
0
Advance Information
2
0
3
0
PGD = Input
4
0
P5
1
0
Data Payload
2
0
16-bit
4.1.3
Regardless of whether high or low-voltage ICSP is
used, it is possible to erase one row (64 bytes of data),
provided the block is not code or write-protected. Rows
are located at static boundaries, beginning at program
memory address 000000h, extending to the internal
program memory limit (see Section 3.0 “Memory
Maps”).
The Row Erase duration is self-timed. After the WR bit
in EECON1 is set, two NOPs are issued. Erase starts
upon the 4th PGC of the second NOP. It ends when the
WR bit is cleared by hardware.
The code sequence to Row Erase a PIC18F1XK50/
PIC18LF1XK50 device is shown in Table 4-3. The flow-
chart shown in Figure 4-3 depicts the logic necessary to
completely erase the PIC18F1XK50/PIC18LF1XK50
devices. The timing diagram for Row Erase is identical
to the data EEPROM write timing, shown in Figure 4-7.
15 16
0
Note 1: The TBLPTR register can point at any
0
P5A
2: ICSP row erase of the User ID locations
4-bit Command
1
ICSP ROW ERASE
0
byte within the row intended for erase.
is also possible using the technique
described in Section 4.1.3 “ICSP Row
Erase”. The address argument used
should be 0x200000. A row erase of the
User ID locations is required when V
below the Bulk Erase threshold.
2
0
3
0
4
0
Erase Time
P11
DS41342E-page 13
P10
Data Payload
1
16-bit
n
2
DD
n
is