PIC18F13K50-I/SS Microchip Technology, PIC18F13K50-I/SS Datasheet - Page 25

• Manufacturer Part Number: PIC18F13K50-I/SS
• Description: IC PIC MCU FLASH 8KB 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3
A Configuration address may be read and output on
PGD via the 4-bit command, ‘1001’. Configuration data
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate Configuration data in the
programmer’s memory for verification. Refer to
Section 5.1 “Read Program Flash, ID Locations and
Configuration Bits” for implementation details of
reading Configuration data.
5.4
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair EEADRH:EEADR) and a
data latch (EEDATA). Data EEPROM is read by
loading EEADRH: EEADR with the desired memory
location and initiating a memory read by appropriately
configuring the EECON1 register. The data will be
loaded into EEDATA, where it may be serially output on
PGD via the 4-bit command, ‘0010’ (Shift Out Data
Holding register). A delay of P6 must be introduced
after the falling edge of the 8th PGC of the operand to
allow PGD to transition from an input to an output.
During this time, PGC must be held low, as shown in
Figure 5-4.
The command sequence to read a single byte of data
is shown in Table 5-2.
TABLE 5-2:
 2010 Microchip Technology Inc.
Step 1: Direct access to data EEPROM.
Step 2: Set the data EEPROM Address Pointer.
Step 3: Initiate a memory read.
Step 4: Load data into the Serial Data Holding register.
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010
4-bit
Verify Configuration Bits
Read Data EEPROM Memory
The <LSB> is undefined. The <MSB> is the data.
READ DATA EEPROM MEMORY
<MSB><LSB>
Data Payload
OE <AddrH>
0E <Addr>
9C A6
6E AA
9E A6
6E A9
6E F5
80 A6
50 A8
00 00
PIC18F1XK50/PIC18LF1XK50
BCF EECON1, EEPGD
BCF EECON1, CFGS
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
BSF EECON1, RD
MOVF EEDATA, W, 0
MOVWF TABLAT
NOP
Shift Out Data
Advance Information
(1)
FIGURE 5-3:
Core Instruction
No
Move to TABLAT
Shift Out Data
READ DATA EEPROM
FLOW
Address
done?
Read
Byte
Start
Done
Set
Yes
DS41342E-page 25