ATTINY85-20PU Atmel, ATTINY85-20PU Datasheet - Page 149
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ATTINY85-20PU
Manufacturer Part Number
ATTINY85-20PU
Description
IC AVR MCU 8K 20MHZ 8DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets
1.ATTINY25-20MU.pdf
(236 pages)
2.ATTINY25-20PU.pdf
(30 pages)
3.ATTINY85-20PU.pdf
(234 pages)
Specifications of ATTINY85-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Controller Family/series
AVR Tiny
No. Of I/o's
6
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
512Byte
# I/os (max)
6
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
8
Package Type
PDIP
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY85-20PU
Manufacturer:
CUI
Quantity:
1 000
19.7
19.8
19.9
19.9.1
2586M–AVR–07/10
Preventing Flash Corruption
Programming Time for Flash when Using SPM
Register Description
SPMCSR – Store Program Memory Control and Status Register
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
The calibrated RC Oscillator is used to time Flash accesses.
gramming time for Flash accesses from the CPU.
Table 19-1.
Note:
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and always read as zero.
• Bit 5 – RSIG: Read Device Signature Imprint Table
Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in
SPMCSR will return the selected data (depending on Z-pointer value) from the device signature
imprint table into the destination register. See
details.
Bit
0x37
Read/Write
Initial Value
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
2. Keep the AVR core in Power-down sleep mode during periods of low V
This can be done by enabling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low V
can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
1. Minimum and maximum programming time is per individual operation.
SPM Programming Time
Symbol
R
7
–
0
CC
, the Flash program can be corrupted because the supply voltage is
R
6
–
0
RSIG
R/W
5
0
(1)
Min Programming Time
CTPB
R/W
4
0
“Device Signature Imprint Table” on page 153
3.7 ms
RFLB
R/W
3
0
PGWRT
Table 19-1
R/W
2
0
CC
reset protection circuit
PGERS
Max Programming Time
R/W
1
0
shows the typical pro-
CC
. This will pre-
4.5 ms
SPMEN
R/W
0
0
SPMCSR
149
for