PIC18F24J10-I/SO Microchip Technology, PIC18F24J10-I/SO Datasheet - Page 327
![IC PIC MCU FLASH 8KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F24J10-I/SO
Manufacturer Part Number
PIC18F24J10-I/SO
Description
IC PIC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18F44J10-IPT.pdf
(358 pages)
Specifications of PIC18F24J10-I/SO
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
SPI, I2C, MSSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18F44J10-IPT PDF datasheet #6
- Current page: 327 of 358
- Download datasheet (6Mb)
FIGURE 23-18:
TABLE 23-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 23-19:
TABLE 23-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
© 2007 Microchip Technology Inc.
120
121
122
Param.
125
126
Param
No.
No.
Note:
RX/DT
TX/CK
T
T
T
Note:
T
T
CK
CKRF
Symbol
DTRF
RX/DT
TX/CK
CK
Symbol
DT
pin
pin
H2
L2
V2
pin
pin
DT
DTL
CKL
Refer to Figure 23-3 for load conditions.
V SYNC XMIT (MASTER and SLAVE)
Refer to Figure 23-3 for load conditions.
Clock High to Data Out Valid
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
SYNC RCV (MASTER and SLAVE)
Data Hold before CK ↓ (DT hold time)
Data Hold after CK ↓ (DT hold time)
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
120
Characteristic
121
Characteristic
125
Preliminary
121
PIC18F45J10 FAMILY
126
Min
10
15
Min
Max
—
—
—
—
—
122
Units
Max
ns
ns
40
20
20
Units
ns
ns
ns
DS39682C-page 325
Conditions
Conditions
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