PIC18F24J10-I/SO Microchip Technology, PIC18F24J10-I/SO Datasheet - Page 126
![IC PIC MCU FLASH 8KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F24J10-I/SO
Manufacturer Part Number
PIC18F24J10-I/SO
Description
IC PIC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18F44J10-IPT.pdf
(358 pages)
Specifications of PIC18F24J10-I/SO
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
SPI, I2C, MSSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18F44J10-IPT PDF datasheet #6
- Current page: 126 of 358
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
13.1
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
13.1.1
The CCP modules utilize Timers 1 or 2, depending on
the mode selected. Timer1 is available to modules in
Capture or Compare modes, while Timer2 is available
for modules in PWM mode.
TABLE 13-1:
TABLE 13-2:
DS39682C-page 124
CCP1 Mode CCP2 Mode
Note 1:
Compare
Compare
Compare
Capture
Capture
Capture
PWM
PWM
PWM
ECCP/CCP Mode
Compare
Capture
(1)
(1)
(1)
CCP Module Configuration
PWM
Includes standard and Enhanced PWM operation.
CCP MODULES AND TIMER
RESOURCES
Compare
Compare
Compare
Capture
Capture
Capture
PWM
PWM
ECCP/CCP MODE – TIMER
INTERACTIONS BETWEEN ECCP1/CCP1 AND CCP2 FOR TIMER RESOURCES
RESOURCE
PWM
(1)
(1)
CCP2 can be configured for the Special Event Trigger to reset TMR1. Automatic A/D
conversions on the trigger event can also be done. Operation of ECCP1/CCP1 will be
affected.
ECCP1/CCP1 can be configured for the Special Event Trigger to reset TMR1. Operation
of CCP2 will be affected.
Either module can be configured for the Special Event Trigger to reset TMR1. Automatic
A/D conversions on the CCP2 trigger event can be done.
None
None
None
None
Each module uses TMR1 as the time base.
Both PWMs will have the same frequency and update rate (TMR2 interrupt).
Timer Resource
Timer1
Timer1
Timer2
Preliminary
Both modules may be active at any given time and may
share the same timer resource if they are configured to
operate in the same mode (Capture/Compare or PWM)
at the same time. The interactions between the two
modules
Figure 13-2. In Timer1 in Asynchronous Counter mode,
the capture operation will not work.
13.1.2
The pin assignment for CCP2 (Capture input, Compare
and PWM output) can change, based on device config-
uration. The CCP2MX configuration bit determines
which pin CCP2 is multiplexed to. By default, it is
assigned to RC1 (CCP2MX = 1). If the configuration bit
is cleared, CCP2 is multiplexed with RB3.
Changing the pin assignment of CCP2 does not auto-
matically change any requirements for configuring the
port pin. Users must always verify that the appropriate
TRIS register is configured correctly for CCP2
operation regardless of where it is located.
Interaction
are
CCP2 PIN ASSIGNMENT
summarized
© 2007 Microchip Technology Inc.
in
Figure 13-1
and
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