ATTINY85-20SU Atmel, ATTINY85-20SU Datasheet - Page 73

• Manufacturer Part Number: ATTINY85-20SU
• Description: IC AVR MCU 8K 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY85-20SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.6.1
2586M–AVR–07/10
Compare Output Mode and Waveform Generation
Figure 11-6. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform
Generator if either of the COM0x[1:0] bits are set. However, the OC0x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi-
ble on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the out-
put is enabled. Note that some COM0x[1:0] bit settings are reserved for certain modes of
operation.
The Waveform Generator uses the COM0x[1:0] bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM0x[1:0] = 0 tells the Waveform Generator that no action
on the OC0x Register is to be performed on the next Compare Match. For compare output
actions in the non-PWM modes refer to
Table 11-3 on page
A change of the COM0x[1:0] bits state will have effect at the first Compare Match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOC0x strobe bits.
COMnx1
COMnx0
FOCn
clk
I/O
See “Register Description” on page 80.
Waveform
Generator
81, and for phase correct PWM refer to
Table 11-2 on page
D
D
D
PORT
DDR
OCnx
Q
Q
Q
Table 11-4 on page
80. For fast PWM mode, refer to
1
0
81.
OCn
Pin
73