PIC16F883-I/SS Microchip Technology, PIC16F883-I/SS Datasheet - Page 119
![IC PIC MCU FLASH 4KX14 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16F883-I/SS
Manufacturer Part Number
PIC16F883-I/SS
Description
IC PIC MCU FLASH 4KX14 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.MCP1631RD-MCC2.pdf
(328 pages)
3.PIC16F882-ISS.pdf
(16 pages)
4.PIC16F882-ISS.pdf
(36 pages)
5.PIC16F883-ISO.pdf
(288 pages)
Specifications of PIC16F883-I/SS
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
MSSP/EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164120-3
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
28SSOP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCP1631RD-MCC2 - REFERENCE DESIGN MCP1631HVAC164307 - MODULE SKT FOR PM3 28SSOPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F883-I/SS
Manufacturer:
ALPS
Quantity:
12 000
Company:
Part Number:
PIC16F883-I/SS
Manufacturer:
Microchip Technology
Quantity:
28 573
Company:
Part Number:
PIC16F883-I/SS
Manufacturer:
MIC
Quantity:
11
Part Number:
PIC16F883-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
10.2
Flash program memory may only be written to if the
destination address is in a segment of memory that is
not write-protected, as defined in bits WRT<1:0> of the
Configuration Word Register 2. Flash program memory
must be written in eight-word blocks (four-word blocks
for 4K memory devices). See Figures 10-2 and 10-3 for
more details. A block consists of eight words with
sequential addresses, with a lower boundary defined by
an address, where EEADR<2:0> = 000. All block writes
to program memory are done as 16-word erase by
eight-word write operations. The write operation is
edge-aligned and cannot occur across boundaries.
To write program data, it must first be loaded into the
buffer registers (see Figure 10-2). This is accomplished
by first writing the destination address to EEADR and
EEADRH and then writing the data to EEDATA and
EEDATH. After the address and data have been set up,
then the following sequence of events must be
executed:
1.
2.
3.
All eight buffer register locations should be written to
with correct data. If less than eight words are being writ-
ten to in the block of eight words, then a read from the
program memory location(s) not being written to must
be performed. This takes the data from the program
location(s) not being written and loads it into the
EEDATA and EEDATH registers. Then the sequence of
events to transfer data to the buffer registers must be
executed.
To transfer data from the buffer registers to the program
memory, the EEADR and EEADRH must point to the last
location in the eight-word block (EEADR<2:0> = 111).
Then the following sequence of events must be
executed:
1.
2.
3.
The user must follow the same specific sequence to
initiate the write for each word in the program block,
writing each program word in sequence (000, 001,
010, 011, 100, 101, 110, 111). When the write is
performed on the last word (EEADR<2:0> = 111), a
block of sixteen words is automatically erased and the
content of the eight word buffer registers are written
into the program memory.
© 2007 Microchip Technology Inc.
Set the EEPGD control bit of the EECON1
register.
Write 55h, then AAh, to EECON2 (Flash
programming sequence).
Set the WR control bit of the EECON1 register.
Set the EEPGD control bit of the EECON1
register.
Write 55h, then AAh, to EECON2 (Flash
programming sequence).
Set control bit WR of the EECON1 register to
begin the write operation.
Writing to Flash Program Memory
PIC16F882/883/884/886/887
Preliminary
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOP instructions after the WR
bit is set. Since data is being written to buffer registers,
the writing of the first seven words of the block appears
to occur immediately. The processor will halt internal
operations for the typical 4 ms, only during the cycle in
which the erase takes place (i.e., the last word of the
sixteen-word block erase). This is not Sleep mode as
the clocks and peripherals will continue to run. After the
eight-word write cycle, the processor will resume oper-
ation with the third instruction after the EECON1 write
instruction. The above sequence must be repeated for
the higher eight words.
DS41291D-page 117