PIC16F616-I/SL Microchip Technology, PIC16F616-I/SL Datasheet
PIC16F616-I/SL
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PIC16F616-I/SL Summary of contents
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... Microchip Technology Inc. PIC16F610/16HV610 PIC16F616/16HV616 Data Sheet 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS41288F ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected - Timer1 oscillator TM • In-Circuit Serial Programming (ICSP Pins PIC16F616/16HV616 only: • A/D Converter: - 10-bit resolution - 8 external input channels - 2 internal reference channels • Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • ...
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... PIC16F610/616/16HV610/616 Program Memory Data Memory Device Flash SRAM (bytes) (words) PIC16F610 1024 PIC16HV610 1024 PIC16F616 2048 PIC16HV616 2048 PIC16F610/16HV610 14-Pin Diagram (PDIP, SOIC, TSSOP RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V PP RC5 RC4/C2OUT RC3/C12IN3- TABLE 1: PIC16F610/16HV610 I/O Pin Comparators RA0 13 C1IN+ RA1 12 C12IN0- RA2 11 C1OUT ...
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... PIC16F616/16HV616 14-Pin Diagram (PDIP, SOIC, TSSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V PP RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/C12IN3-/P1C TABLE 2: PIC16F616/16HV616 I/O Pin Analog Comparators RA0 13 AN0 C1IN+ RA1 12 AN1/V C12IN0- REF RA2 11 AN2 C1OUT (1) RA3 4 — — RA4 3 AN3 — RA5 2 — — RC0 10 AN4 C2IN+ ...
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... Basic ICSPDAT ICSPCLK — MCLR/V PP OSC2/CLKOUT OSC1/CLKIN — — — — — — © 2009 Microchip Technology Inc. ...
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... PIC16F616/16HV616 16-Pin Diagram (QFN) RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V PP RC5/CCP/P1A TABLE 4: PIC16F616/16HV616 I/O Pin Analog Comparators RA0 12 AN0 C1IN+ RA1 11 AN1/V C12IN0- REF RA2 10 AN2 C1OUT (1) RA3 3 — — RA4 2 AN3 — RA5 1 — — RC0 9 AN4 C2IN+ RC1 8 AN5 C12IN1- RC2 7 AN6 ...
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... Timer2 Module (PIC16F616/16HV616 only) ............................................................................................................................. 55 8.0 Comparator Module ................................................................................................................................................................... 57 9.0 Analog-to-Digital Converter (ADC) Module (PIC16F616/16HV616 only) .................................................................................. 73 10.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC16F616/16HV616 Only) .................. 85 11.0 Voltage Regulator .................................................................................................................................................................... 107 12.0 Special Features of the CPU ................................................................................................................................................... 109 13.0 Instruction Set Summary .......................................................................................................................................................... 129 14.0 Development Support............................................................................................................................................................... 139 15 ...
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... The PIC16F610/616/16HV610/616 is covered by this data sheet available in 14-pin PDIP, SOIC, TSSOP and 16-pin QFN packages. Block Diagrams and pinout descriptions of the devices are as follows: • PIC16F610/16HV610 (Figure 1-1, Table 1-1) • PIC16F616/16HV616 (Figure 1-2, Table 1-2) FIGURE 1-1: PIC16F610/16HV610 BLOCK DIAGRAM Configuration Flash ...
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... PIC16F610/616/16HV610/616 FIGURE 1-2: PIC16F616/16HV616 BLOCK DIAGRAM Configuration Flash Program Memory Program 14 Bus Instruction Reg 8 Instruction Decode and Control Timing OSC1/CLKIN Generation OSC2/CLKOUT Internal Oscillator Block T1G T1CKI Timer0 T0CKI Analog-To-Digital Converter DS41288F-page 10 INT 13 Data Bus Program Counter RAM 8-Level Stack 128 Bytes ...
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... RC0/C2IN+ RC1/C12IN1- RC2/C12IN2- RC3/C12IN3- RC4/C2OUT RC5 Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Input Output Type Type RA0 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change C1IN+ AN — Comparator C1 non-inverting input ...
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... PIC16F610/616/16HV610/616 TABLE 1-2: PIC16F616/16HV616 PINOUT DESCRIPTION Name Function RA0/AN0/C1IN+/ICSPDAT RA1/AN1/C12IN0-/V /ICSPCLK REF RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/V PP RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RC0/AN4/C2IN+ RC1/AN5/C12IN1- RC2/AN6/C12IN2-/P1D RC3/AN7/C12IN3-/P1C RC4/C2OUT/P1B RC5/CCP1/P1A Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL DS41288F-page 12 Input Output Type Type ...
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... PIC16F610/616/16HV610/616 program counter capable of addressing program memory space. Only the first (0000h-3FF) for the PIC16F610/16HV610 and the first (0000h-07FFh) for the PIC16F616/16HV616 is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first space (PIC16F610/16HV610) and space (PIC16F616/16HV616). The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1) ...
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... DS41288F-page 14 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized the PIC16F610/16HV610 PIC16F616/16HV616. Each register is accessed, either directly or indirectly, through the File Select Reg- each bank. ister (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). Register 2 ...
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... ADCON0 A0h General Purpose Registers 96 Bytes F0h FFh Bank 0 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. DATA MEMORY MAP OF THE PIC16F616/16HV616 File File Address Address (1) (1) Indirect Addr. 00h 80h OPTION_REG 01h 81h 02h PCL ...
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... ADCON0 ADFM VCFG Legend: – = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: PIC16F616/16HV616 only. 3: Read-only register. DS41288F-page 16 Bit 5 Bit 4 Bit 3 Bit 2 RP0 TO PD ...
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... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. 3: PIC16F616/16HV616 only. 4: Read-only Register. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 5 Bit 4 ...
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... The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. R-1 R-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. used by the and R/W-x R/W bit Bit is unknown ...
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... Microchip Technology Inc. PIC16F610/616/16HV610/616 Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 5.1.3 “Software Programmable Prescaler”. ...
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... R/W-0 R/W-0 R/W-0 INTE RAIE T0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) should ensure the R/W-0 R/W-0 INTF RAIF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software Timer1 has not overflowed Note 1: PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’. DS41288F-page 22 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Reads as ‘0’ if Brown-out Reset is disabled. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 U-0 U-0 U-0 — — ...
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... Example 2-1. EXAMPLE 2-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE INDIRECT ADDRESSING 0x40 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR, F ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue © 2009 Microchip Technology Inc. ...
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... Unimplemented data memory locations, read as ‘0’. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. 2: Accesses in Bank 2 and Bank 3 are mirrored back into Bank 0 and Bank 1, respectively. FIGURE 2-7: DIRECT/INDIRECT ADDRESSING PIC16F616/16HV616 Direct Addressing (1) RP1 RP0 ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 26 © 2009 Microchip Technology Inc. ...
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... PIC MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator OSC2 Sleep OSC1 Internal Oscillator INTOSC 8 MHz © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode. 3. ...
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... These oscillator delays are shown in Table 3-1. ® MCU (1) Frequency 4 MHz to 8 MHz DC – 20 MHz 32 kHz to 20 MHz Oscillator Delay Oscillator Warm-Up Delay (T ) WARM 2 Instruction Cycles 1024 Clock Cycles (OST) © 2009 Microchip Technology Inc. ...
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... The value of R varies with the Oscillator mode F selected (typically between 2 MΩ MΩ). © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application ...
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... The CLKOUT Clock signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O. ) values EXT See Section 12.0 “Special © 2009 Microchip Technology Inc. ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 12-1) for operation of all register bits. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 32 © 2009 Microchip Technology Inc. ...
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... Note 1: TRISA<3> always reads ‘1’. 2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. ...
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... Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: PIC16F616/HV616. DS41288F-page 34 4.2.3 INTERRUPT-ON-CHANGE Each PORTA pin is individually configurable as an interrupt-on-change pin ...
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... IOCA<5:0>: Interrupt-on-change PORTA Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-1 U-0 R/W-1 WPUA4 — ...
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... Figure 4-1 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • an analog inverting input to the comparator • a voltage reference input for the ADC • In-Circuit Serial Programming clock Note 1: PIC16F616/16HV616 only. Analog Input Mode ...
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... IOAC RD IOAC ( Interrupt-on- From other Change R RA<5:3, 1:0> pins Write ‘0’ to RAIF Note 1: Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Analog Input Mode C1OE Enable C1OE ...
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... BLOCK DIAGRAM OF RA3 Data Bus RD TRISA RD PORTA WR IOCA RD IOCA ( Interrupt-on- From other Change R RA<5:4, 2:0> pins Write ‘0’ to RAIF Note 1: Set has priority over Reset DS41288F-page 38 MCLRE Reset PORTA V DD Weak MCLRE Input Pin MCLRE © 2009 Microchip Technology Inc. ...
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... With CLKOUT option. 3: Analog Input mode comes from ANSEL. 4: Set has priority over Reset. 5: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 • a Timer1 gate (count enable) • a crystal/resonator connection • a clock output Note 1: PIC16F616/16HV616 only. Analog Input Mode Data Bus ...
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... INTOSC Mode Data Bus WPUA RAPU RD WPUA Oscillator Circuit OSC2 PORTA TRISA INTOSC RD Mode TRISA RD PORTA IOCA RD IOCA From other RA<4:0> pins RD PORTA To Timer1 (1) TMR1LPEN V DD Weak V DD I/O Pin © 2009 Microchip Technology Inc. ...
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... TRISA — — TRISA5 WPUA — — WPUA5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: For PIC16F616/HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 (1) (1) ANS4 ANS3 ANS2 ...
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... Bit is cleared INITIALIZING PORTC ;Bank 0 ;Init PORTC ;Bank 1 ;digital I/O ;Set RC<3:2> as inputs ;and set RC<5:4,1:0> ;as outputs ;Bank 0 R/W-0 R/W-x R/W-x RC2 RC1 RC0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISC2 TRISC1 TRISC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Comparator C2 (1) 4.3.2 RC1/AN5 /C12IN1- The RC1 is configurable to function as one of the following: • a general purpose I/O (1) • an analog input for the ADC • an analog inverting input to the comparator Note 1: PIC16F616/16HV616 only. FIGURE 4-6: BLOCK DIAGRAM OF RC0 AND RC1 Data Bus PORTC ...
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... Shaded cells are not used by PORTC. Note 1: PIC16F616/HV616 only. DS41288F-page 44 4.3.6 RC5/CCP1 The RC5 is configurable to function as one of the following: • a general purpose I/O • a digital input/output for the Enhanced CCP (1) Note 1: PIC16F616/16HV616 only. FIGURE 4-9: Data bus PORTC D Q ...
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... Watchdog WDTE Timer Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in the Configuration Word register. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. ...
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... T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 15.0 “Electrical Specifications”. © 2009 Microchip Technology Inc. ...
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... T0CS TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 48 © 2009 Microchip Technology Inc. ...
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... ST Buffer is low power type when using LP osc, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 6.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair ...
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... Note: In asynchronous counter mode or when using the internal oscillator and T1ACS=1, Timer1 can not be used as a time base for the capture or compare modes of the ECCP module (for PIC16F616/HV616 only). 6.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...
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... TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 10.0 “Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC16F616/16HV616 Only)”. 6.10 ECCP Special Event Trigger (PIC16F616/16HV616 Only) When the ECCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair ...
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... If INTOSC without CLKOUT oscillator is active oscillator is enabled for Timer1 clock oscillator is off Else: This bit is ignored DS41288F-page 52 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register Timer1 gate source. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 DS41288F-page 53 ...
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... Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1CON T1GINV TMR1GE T1CKPS1 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: PIC16F616/16HV616 only. DS41288F-page 54 Bit 4 Bit 3 Bit 2 Bit 1 C2POL — C2R ...
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... TIMER2 MODULE (PIC16F616/16HV616 ONLY) The Timer2 module is an 8-bit timer with the following features: • 8-bit timer register (TMR2) • 8-bit period register (PR2) • Interrupt on TMR2 match with PR2 • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) See Figure 7-1 for a block diagram of Timer2 ...
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... Holding Register for the 8-bit TMR2 Register (1) T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 Legend unknown unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. Note 1: PIC16F616/16HV616 only. DS41288F-page 56 R/W-0 R/W-0 R/W-0 TOUTPS1 TOUTPS0 TMR2ON U = Unimplemented bit, read as ‘0’ ...
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... When the analog voltage at V less than the analog voltage the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 8- ...
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... IN C2SYNC C2POL D Q From Timer1 Clock C1POL To Data Bus RD_CM1CON0 Set C1IF PWM Logic CL C1OE (2) C1OUT pin C2POL To Data Bus RD_CM2CON0 Set C2IF other peripherals C2OE 0 MUX 1 (2) C2OUT pin SYNCC2OUT To Timer1 Gate To SR Latch © 2009 Microchip Technology Inc. ...
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... See Section 8.11 “Comparator Voltage Reference” for more information on the internal voltage reference module. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.2.4 COMPARATOR OUTPUT SELECTION The output of the comparator can be monitored by ...
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... Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. © 2009 Microchip Technology Inc. reset by software ...
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... INTCON register is also set, the device will then execute the interrupt service routine. 8.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their OFF states. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 DS41288F-page 61 ...
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... Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port TRIS bit = 0. DS41288F-page 62 R/W-0 U-0 C1POL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > C1V - < C1V - > C1V - < C1V - IN IN (1) output REF - R/W-0 R/W-0 R/W-0 C1R C1CH1 C1CH0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... C2 connects to C12IN2 C2V - pin of C2 connects to C12IN3- IN Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 U-0 C2POL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > ...
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... V . The SS 2: Analog levels on any pin defined as a and digital input, may cause the input buffer to consume more current than is specified ≈ 0. LEAKAGE ≈ 0. ±500 nA Vss To ADC Input © 2009 Microchip Technology Inc. ...
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... Timer1 gate source is T1G 0 = Timer1 gate source is SYNCC2OUT. bit 0 C2SYNC: Comparator C2 Output Synchronization bit Output is synchronous to falling edge of Timer1 clock Output is asynchronous © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.8.2 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1 The Comparator C2 output can be synchronized with Timer1 by setting the C2SYNC bit of the CM2CON1 register ...
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... V + rises above the upper IN hysteresis threshold (V +). The output of the H comparator changes from a high state to a low state only when the analog voltage at V lower hysteresis threshold (V + Output – © 2009 Microchip Technology Inc. + falls below the IN -). H ...
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... TRISA5 TRISC TRISC5 VRCON C1VREN C2VREN VRR Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 (1) (1) ANS4 ANS3 ANS2 ANS1 ...
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... The latch configuration enable states are completely independent of the enable states for the comparators. SR0 (1) Latch R Q SR1 pulse width. OSC C1OE 0 MUX 1 (3) C1OUT pin C2OE 1 MUX 0 (3) C2OUT pin © 2009 Microchip Technology Inc. ...
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... SRCS<1:0>: SR Latch Clock Prescale bits /16 OSC /32 OSC /64 OSC /128 OSC bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 R/S-0 R/S-0 C2REN PULSS PULSR S = Bit is set only - U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) U-0 U-0 U-0 — ...
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... OUTPUT RATIOMETRIC TO VDD The comparator voltage reference is V therefore, the The tested absolute accuracy of the Comparator DD Voltage Reference can be found in Section 15.0 “Electrical Specifications”. DD × /32 derived and DD output changes with fluctuations in REF © 2009 Microchip Technology Inc. ...
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... REF To Comparators and ADC Module C1VREN C2VREN To ADC Module Fixed Ref To Comparators and ADC Module © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.11.7 VOLTAGE REFERENCE SELECTION , with DD Multiplexers on the output of the voltage reference module enable selection of either the CV voltage reference for use by the comparators. ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared input of Comparator C1 REF input of Comparator C1 REF input of Comparator C2 REF input of Comparator C2 REF Value Selection bits (0 ≤ VR<3:0> ≤ 15) REF = (VR<3:0>/24 (VR<3:0>/32 R/W-0 R/W-0 VR2 VR1 VR0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE (PIC16F616/16HV616 ONLY) The Analog-to-Digital Converter conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter ...
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... DD ) OSC 4 MHz 1 MHz (2) 2.0 μs 500 ns 1.0 μs (2) 4.0 μs 2.0 μs 8.0 μs (3) 4.0 μs 16.0 μs (3) 8.0 μs (3) 32.0 μs (3) 16.0 μs 64.0 μs (3) (3) 2-6 μs 2-6 μs (1,4) (1,4) © 2009 Microchip Technology Inc. ...
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... Please see Section 9.1.5 “Interrupts” for more information. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT (ADFM = 0) MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 CYCLES ...
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... ADC timing the user’s responsibility to ensure that the ADC timing requirements are met. See Section 10.0 “Enhanced Capture/Compare/ PWM (With Auto-Shutdown and Dead Band) Module (PIC16F616/16HV616 Only)” for more information. 9.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an analog-to-digital conversion: 1 ...
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... BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 DS41288F-page 77 ...
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... If the Comparator module uses this VP6 reference voltage, the comparator output may momentarily change state due to the transient. DS41288F-page 78 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 79
... RC 100 = F /4 OSC 101 = F /16 OSC 110 = F /64 OSC bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — ...
Page 80
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-x R-x ADRES3 ADRES2 bit Bit is unknown U-0 U-0 — — bit Bit is unknown R-x R-x ADRES9 ADRES8 bit Bit is unknown R-x R-x ADRES1 ADRES0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 81
... Note 1: The reference voltage (V REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 ) SS ) impedance SS = 50°C and external impedance of 10k ...
Page 82
... REF DS41288F-page Sampling Switch V = 0.6V T ≤ Rss LEAKAGE V = 0.6V T ± 500 Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal Zero-Scale REF Transition HOLD REF Sampling Switch (kΩ) © 2009 Microchip Technology Inc. ...
Page 83
... TRISA5 TRISC — — TRISC5 Legend unknown unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Note 1: PIC16F616/16HV616 only. 2: Read-only Register. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 ...
Page 84
... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 84 © 2009 Microchip Technology Inc. ...
Page 85
... ENHANCED CAPTURE/ COMPARE/PWM (WITH AUTO- SHUTDOWN AND DEAD BAND) MODULE (PIC16F616/16HV616 ONLY) The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external ...
Page 86
... NEW_CAPT_PS ;Load the W reg with CCPR1L MOVWF CCP1CON TMR1L of the CCP1CON register. CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value © 2009 Microchip Technology Inc. ...
Page 87
... TRISA5 TRISC — — TRISC5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 ...
Page 88
... CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. the match condition by © 2009 Microchip Technology Inc. ...
Page 89
... TRISA5 TRISC — — TRISC5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 ...
Page 90
... In PWM mode, CCPR1H is a read-only register. DS41288F-page 90 The PWM output (Figure 10-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 10-4: Period Pulse Width TMR2 = 0 CCP1 TRIS ), or OSC CCP PWM OUTPUT TMR2 = PR2 TMR2 = CCPR1L:CCP1CON<5:4> © 2009 Microchip Technology Inc. ...
Page 91
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) 16 PR2 Value 0x65 Maximum Resolution (bits) 8 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 EQUATION 10-2: Pulse Width EQUATION 10-3: • OSC Duty Cycle Ratio The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle ...
Page 92
... Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output by clearing the associated TRIS bit. © 2009 Microchip Technology Inc. ...
Page 93
... Full-Bridge, Forward 01 Full-Bridge, Reverse 11 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. ...
Page 94
... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 10.4.6 “Programmable Dead-Band Delay mode”). DS41288F-page 94 Pulse 0 Width Period (1) (1) Delay Delay © 2009 Microchip Technology Inc. PR2+1 ...
Page 95
... OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 10.4.6 “Programmable Dead-Band Delay mode”). © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Pulse 0 Width Period (1) (1) Delay Delay ...
Page 96
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FET Driver P1A Load FET Driver P1B V+ FET Driver Load FET Driver EXAMPLE OF HALF- BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2009 Microchip Technology Inc. ...
Page 97
... EXAMPLE OF FULL-BRIDGE APPLICATION P1A P1B P1C P1D © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. ...
Page 98
... EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41288F-page 98 Period (1) Period (1) © 2009 Microchip Technology Inc. ...
Page 99
... When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer2 counts. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 The Full-Bridge mode does not provide dead-band delay ...
Page 100
... Potential Shoot-Through Current Note 1: All signals are shown as active-high the turn on delay of power switch QC and its driver the turn off delay of power switch QD and its driver. OFF DS41288F-page 100 Forward Period Reverse Period OFF – T OFF ON © 2009 Microchip Technology Inc. ...
Page 101
... Output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 DS41288F-page 101 ...
Page 102
... Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 PSSBD1 PSSBD0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 103
... FIGURE 10-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) Shutdown Event ECCPASE bit PWM Activity Start of PWM Period © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 condition PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM ...
Page 104
... P1B ( Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high OSC V+ FET Driver P1A Load FET Driver P1B V- EXAMPLE OF HALF- BRIDGE PWM OUTPUT Period Period td (1) ( © 2009 Microchip Technology Inc. ...
Page 105
... TRISC — — TRISC5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ...
Page 106
... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 106 © 2009 Microchip Technology Inc. ...
Page 107
... See Figure 11-1 for voltage regulator schematic. FIGURE 11-1: VOLTAGE REGULATOR V UNREG R I SER SUPPLY I SHUNT C Feedback BYPASS © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 An external current limiting resistor, R between the unregulated supply, V pin, drops the difference in voltage between V and SER defined by Equation 11- EQUATION 11-1: supply current ...
Page 108
... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 108 © 2009 Microchip Technology Inc. ...
Page 109
... The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 12-1). © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.1 Configuration Bits The Configuration bits can be programmed (read as ‘ ...
Page 110
... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS41288F-page 110 — — (3) PWRTE WDTE FOSC2 P = Programmable’ ‘0’ = Bit is cleared (1) (2) (3) (1) (1) — BOREN1 BOREN0 bit 8 FOSC1 FOSC0 bit Unimplemented bit, read as ‘0’ Bit is unknown DD © 2009 Microchip Technology Inc. ...
Page 111
... CLKI pin PWRT On-Chip 11-bit Ripple Counter RC OSC Note 1: Refer to the Configuration Word register (Register 12-1). © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 • Power-on Reset • MCLR Reset • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (BOR) WDT wake-up does not cause register resets in the same manner as a WDT Reset since wake-up is viewed as the resumption of normal operation ...
Page 112
... V RECOMMENDED MCLR CIRCUIT DD ® PIC MCU R1 1 kΩ (or greater) R2 MCLR 100 Ω (needed with capacitor) C1 0.1 μF (optional, not critical) for details (Section 15.0 at the MCLR SS Ω should be used when . SS © 2009 Microchip Technology Inc. ...
Page 113
... Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until V above V (see Figure 12-3). If enabled, the Power- BOR up Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms ...
Page 114
... Bit 2 Bit 1 — — — POR may have gone too DD Wake-up from Sleep PWRTE = 1 1024 • T 1024 • T OSC OSC — — Value on Value on Bit 0 all other POR, BOR (1) Resets BOR ---- --qq ---- --uu C 0001 1xxx 000q quuu © 2009 Microchip Technology Inc. ...
Page 115
... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 T PWRT T PWRT T PWRT T OST T OST ) DD T OST DS41288F-page 115 ...
Page 116
... See Table 12-5 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit PIC16F616/16HV616 only. 7: ANSEL <3:2> For PIC16F616/HV616 only. DS41288F-page 116 Wake-up from Sleep through MCLR Reset WDT Reset Wake-up from Sleep through ...
Page 117
... See Table 12-5 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit PIC16F616/16HV616 only. 7: ANSEL <3:2> For PIC16F616/HV616 only. TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Power-on Reset MCLR Reset during normal operation ...
Page 118
... PORTA Change Interrupts • 2 Comparator Interrupts • A/D Interrupt (PIC16F616/16HV616 only) • Timer1 Overflow Interrupt • Timer2 Match Interrupt (PIC16F616/16HV616 only) • Enhanced CCP Interrupt (PIC16F616/16HV616 only) The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits ...
Page 119
... Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 12.7.1 “Wake-up from Sleep”. 2: PIC16F616/16HV616 only. (1) Wake-up (If in Sleep mode) Interrupt to CPU DS41288F-page 119 ...
Page 120
... PIR1 — ADIF CCP1IF (1) (1) PIE1 — ADIE CCP1IE Legend unknown unchanged, – = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by the interrupt module. Note 1: PIC16F616/16HV616 only. DS41288F-page 120 (1) (2) Interrupt Latency Inst ( — Dummy Cycle ...
Page 121
... STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 and DS41288F-page 121 ...
Page 122
... Max. WDT prescaler) it may take several seconds before a WDT Time-out occurs 8-bit Prescaler PSA PS<2:0> 0 PSA = Min., Temperature = Max., DD Data Bus 8 SYNC 2 TMR0 Cycles Set Flag bit T0IF on Overflow WDT Time-Out WDT Cleared Cleared until the end of OST © 2009 Microchip Technology Inc. ...
Page 123
... INTEDG T0CS (1) CONFIG IOSCFS CP MCLRE Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of all Configuration Word register bits. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 T0SE PSA PS2 PS1 PWRTE WDTE ...
Page 124
... To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. See Figure 12-9 for more details. © 2009 Microchip Technology Inc. ...
Page 125
... ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 OST (2) T (3) ...
Page 126
... For more information, see “MPLAB Debugger User’s Guide” (DS51331), available on Microchip’s web site (www.microchip.com). /GP3/RA3 PP must be above DD minimum given in the DD Programming Specification DEBUGGER RESOURCES Description ICDCLK, ICDDATA 1 level Address 0h must be NOP 700h-7FFh ® ICD 2 In-Circuit © 2009 Microchip Technology Inc. ...
Page 127
... DD CS0 2 27 CS1 3 26 CS2 4 25 RA5 5 24 RA4 6 23 RA3 7 22 RC5 8 21 RC4 9 20 RC3 ICDCLK 12 17 ICDMCLR 13 16 ICDDATA 14 15 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 GND RA0 RA1 SHUNTEN RA2 RC0 RC1 RC2 ICD DS41288F-page 127 ...
Page 128
... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 128 © 2009 Microchip Technology Inc. ...
Page 129
... PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unin- tended consequence of clearing the condition that set the RAIF flag. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 13-1: OPCODE FIELD DESCRIPTIONS ...
Page 130
... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2009 Microchip Technology Inc. ...
Page 131
... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 BCF Syntax: k Operands: Operation: Status Affected: ...
Page 132
... Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. ...
Page 133
... Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 INCFSZ Syntax: Operands: Operation: Status Affected: Description: ...
Page 134
... Move label ] MOVWF f 0 ≤ f ≤ 127 (W) → (f) None Move data from W register to register ‘f’ MOVW OPTION F Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F No Operation [ label ] NOP None No operation None No operation NOP © 2009 Microchip Technology Inc. ...
Page 135
... Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 RETLW Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example: TABLE DONE RETURN Syntax: Operands: ...
Page 136
... Subtract W from literal [ label ] SUBLW k 0 ≤ k ≤ 255 k - (W) → (W) The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. Result Condition W > ≤ W<3:0> > k<3:0> W<3:0> ≤ k<3:0> © 2009 Microchip Technology Inc. ...
Page 137
... Operation: Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [ label ] XORWF f,d 0 ≤ ...
Page 138
... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 138 © 2009 Microchip Technology Inc. ...
Page 139
... MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 14.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 140
... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility © 2009 Microchip Technology Inc. ...
Page 141
... Microchip Technology Inc. PIC16F610/616/16HV610/616 14.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...
Page 142
... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® © 2009 Microchip Technology Inc. ...
Page 143
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 ........................................................................... -0. )...............................................................................................................± ...
Page 144
... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC16HV610/616 VOLTAGE-FREQUENCY GRAPH, ≤ ≤ -40°C T +125°C A 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41288F-page 144 8 10 Frequency (MHz Frequency (MHz © 2009 Microchip Technology Inc. ...
Page 145
... FIGURE 15-4: PIC16HV610/616 FREQUENCY TOLERANCE GRAPH, ≤ ≤ -40°C T +125°C A 125 -40 2.0 2.5 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 ± 5% ± 2% ± 1% 3.0 3.5 4.0 4.5 V (V) DD ± 5% ± 2% ± 1% 3.0 3.5 4.0 V (V) DD 5.0 5.5 4.5 5 ...
Page 146
... V/ms See Section 12.3.1 “Power-on Reset (POR)” for details. can be lowered in Sleep mode without losing RAM data. ≤ +85°C for industrial A ≤ +125°C for extended A Conditions < MHz < MHz < MHz < MHz < MHz < MHz < MHz < MHz © 2009 Microchip Technology Inc. ...
Page 147
... For RC oscillator configurations, current through R be extended by the formula I © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 -40°C ≤ T ≤ +85°C for industrial A -40°C ≤ T ≤ ...
Page 148
... OSC LP Oscillator mode MHz OSC XT Oscillator mode MHz OSC XT Oscillator mode MHz OSC EC Oscillator mode MHz OSC EC Oscillator mode MHz OSC INTOSC mode MHz OSC INTOSC mode MHz OSC (3) EXTRC mode MHz OSC HS Oscillator mode © 2009 Microchip Technology Inc. ...
Page 149
... Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 -40°C ≤ T ≤ +85°C for industrial ...
Page 150
... REF T1OSC disabled (1) WDT Current (1) BOR Current (1) Comparator Current , both comparators enabled (1) Comparator Current , single comparator enabled (1) CV Current (high range) REF (1) CV Current (low range) REF (1) T1OSC Current , 32.768 kHz (1) A/D Current , no conversion in progress © 2009 Microchip Technology Inc. ...
Page 151
... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied Shunt regulator is always enabled and always draws operating current. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 - I (Industrial) -40°C ≤ T ≤ ...
Page 152
... REF T1OSC disabled (1) WDT Current (1) BOR Current (1) Comparator Current , both comparators enabled (1) Comparator Current , single comparator enabled (1) CV Current (high range) REF (1) CV Current (low range) REF (1) T1OSC Current , 32.768 kHz (1) A/D Current , no conversion in progress © 2009 Microchip Technology Inc. ...
Page 153
... This specification applies to RA3/MCLR configured as RA3 input with internal pull-up disabled. 5: This specification applies to all weak pull-up pins, including the weak pull-up on RA3/MCLR. When RA3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 PIC16F610/616/16HV610/616 - I (Industrial) ...
Page 154
... A Units Conditions pF In XT, HS and LP modes when external clock is used to drive OSC1 pF -40°C ≤ T ≤ +85°C E/W A +85°C ≤ T ≤ +125°C E Minimum operating MIN voltage V ms Year Provided no other specifications are violated © 2009 Microchip Technology Inc. ...
Page 155
... DER * These parameters are characterized but not tested. Note current to run the chip alone without driving any load on the output pins Ambient Temperature. A © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Typ Units 70* C/W 14-pin PDIP package 85.0* C/W 14-pin SOIC package 100* ...
Page 156
... Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 15-5: LOAD CONDITIONS Load Condition Pin Legend for all pins for OSC2 output DS41288F-page 156 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance L © 2009 Microchip Technology Inc. ...
Page 157
... Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Q1 ...
Page 158
... T ≤ +85°C A 2.0V ≤ V ≤ 5.5V, DD -40°C ≤ T ≤ +85°C (Ind.), A -40°C ≤ T ≤ +125°C (Ext.) A μ 2.0V, -40°C to +85°C DD μ 3.0V, -40°C to +85°C DD μ 5.0V, -40°C to +85°C DD © 2009 Microchip Technology Inc. ...
Page 159
... These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output Includes OSC2 in CLKOUT mode. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Fetch Read Q1 Q2 OS11 ...
Page 160
... Asserted low. FIGURE 15-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) Reset (due to BOR delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. DS41288F-page 160 BOR 37 33 HYST (Device not in Brown-out Reset) © 2009 Microchip Technology Inc. ...
Page 161
... By design. 3: Period of the slower clock ensure these voltage tolerances, V possible. 0.1 μF and 0.01 μF values in parallel are recommended. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 ≤ +125°C Min Typ† Max Units 2 — ...
Page 162
... T — OSC 49 Max Units Conditions — ns — ns — ns — ns — prescale value (2, 4, ..., 256) — ns — ns — ns — ns — ns — ns — prescale value ( — ns — kHz 7 T — Timers in Sync OSC mode © 2009 Microchip Technology Inc. ...
Page 163
... CCP1 Input Period * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 CC01 CC02 CC03 ≤ ...
Page 164
... V – 1 — dB 600 ns 1000 ns μ 1.5)/ mV 1.5V)/2. Units Comments V Low Range (VRR = 1) V High Range (VRR = 0) LSb Low Range (VRR = 1) LSb High Range (VRR = 0) Ω μs -40°C ≤ T ≤ +125°C A Units Comments 0 μs — © 2009 Microchip Technology Inc. ...
Page 165
... Settling Time SETTLE SR04 C Load Capacitance LOAD ΔI SR05 Regulator operating current SNT * These parameters are characterized but not tested. TABLE 15-11: PIC16F616/16HV616 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature A Param Sym Characteristic No. AD01 N Resolution ...
Page 166
... PIC16F610/616/16HV610/616 TABLE 15-12: PIC16F616/16HV616 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature A Param Sym Characteristic No. AD130* T A/D Clock Period AD A/D Internal RC Oscillator Period AD131 T Conversion Time CNV (not including (1) Acquisition Time) AD132* T Acquisition Time ACQ AD133* T ...
Page 167
... OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. FIGURE 15-13: PIC16F616/16HV616 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 ( OSC Q4 A/D CLK A/D Data ADRES ADIF GO ...
Page 168
... PIC16F610/616/16HV610/616 15.13 High Temperature Operation This section outlines the specifications for the PIC16F616 device operating in a temperature range (4) between -40°C and 150°C. The specifications (4) between -40°C and 150°C are identical to those shown in DS41302 and DS80329. Note 1: Writes are not allowed for Flash Program Memory above 125° ...
Page 169
... DD D011 μA D012 μA mA D013 μA D014 μA mA D016 μA μA D017 mA D018 μA D019 mA © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 SPECIFICATIONS FOR PIC16F616 – H (High DD Min Typ Max V DD — 2.0 — 3.0 — 5.0 — 135 316 2.0 — ...
Page 170
... D023E μA μA D024E μA D025E μA D026E μA D027E μA TABLE 15-16: WATCHDOG TIMER SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Param Sym Characteristic No Watchdog Timer Time-out Period WDT (No Prescaler) TABLE 15-17: LEAKAGE CURRENT SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Param ...
Page 171
... INT Int. Calibrated INTOSC OSC (1) Freq. Note 1: To ensure these oscillator frequency tolerances, V the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended. TABLE 15-19: COMPARATOR SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Param Sym Characteristic No. CM01 V Input Offset Voltage OS © ...
Page 172
... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 172 © 2009 Microchip Technology Inc. ...
Page 173
... Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125° FIGURE 16-2: PIC16F610/616 I 600 Typical: Statistical Mean @25°C 500 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 400 300 200 100 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 LP (32 kHz MHz) vs (V) DD Maximum Typical 5 6 Maximum ...
Page 174
... PIC16F610/616 I 1200 Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 800 600 400 200 0 1 DS41288F-page 174 EC (4 MHz MHz MHz) vs (V) DD Maximum Typical 5 6 Maximum Typical 5 6 Maximum Typical 5 6 © 2009 Microchip Technology Inc. ...
Page 175
... FIGURE 16-7: PIC16F610/616 I 1800 Typical: Statistical Mean @25°C 1600 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 1400 1200 1000 800 600 400 200 0 1 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 INTOSC (4 MHz) vs (V) DD INTOSC (8 MHz) vs (V) DD Maximum Typical ...
Page 176
... FIGURE 16-9: PIC16F610/616 I Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) DS41288F-page 176 EXTRC (4 MHz (20 MHz) vs Maximum Typical 6 5 Maximum Typical (V) DD © 2009 Microchip Technology Inc. ...
Page 177
... Extended: Mean (Worst-Case Temp) + 3σ 7 (-40°C to 125° FIGURE 16-11: PIC16F610/616 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 BASE vs (V) DD COMPARATOR (SINGLE ON) vs Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125° (V) DD Extended ...
Page 178
... DS41288F-page 178 COMPARATOR (BOTH ON) vs Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125° (V) DD WDT vs ( Extended Industrial Typical 6 5 Extended Industrial Typical 5 6 © 2009 Microchip Technology Inc. ...
Page 179
... FIGURE 16-15: PIC16F610/616 I 140 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp (-40°C to 85°C) 120 Extended: Mean (Worst-Case Temp (-40°C to 125°C) 100 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 BOR vs σ σ ( (LOW RANGE) vs REF DD σ σ (V) DD Extended Industrial ...
Page 180
... Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 20 (-40°C to 125° DS41288F-page 180 CV (HI RANGE) vs REF DD σ σ VDD (V) T1OSC vs (V) DD Maximum Typical 6 5 Extended Industrial Typical 5 6 © 2009 Microchip Technology Inc. ...
Page 181
... FIGURE 16-18: PIC16F616 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ 12 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 10 (-40°C to 125° FIGURE 16-19: PIC16HV610/616 I 450 Typical: Statistical Mean @25°C 400 Maximum: Mean (Worst-Case Temp) + 3σ 350 (-40°C to 125°C) ...
Page 182
... Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 700 (-40°C to 125°C) 600 500 400 300 200 100 0 1 DS41288F-page 182 EC (1 MHz MHz MHz) vs (V) DD Maximum Typical 5 4 Maximum Typical 5 4 Maximum Typical 5 4 © 2009 Microchip Technology Inc. ...
Page 183
... FIGURE 16-25: PIC16HV610/616 I 2000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 1500 (-40°C to 125°C) 1000 500 0 1 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 XT (4 MHz) vs (V) DD INTOSC (4 MHz) vs (V) DD INTOSC (8 MHz) vs ...
Page 184
... Typical: Statistical Mean @25°C 500 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 400 300 200 100 DS41288F-page 184 EXTRC (4 MHz) vs (V) DD BASE vs (V) DD COMPARATOR (SINGLE ON) vs (V) DD Maximum Typical 5 4 Maximum Typical Maximum Typical 5 4 © 2009 Microchip Technology Inc. ...
Page 185
... FIGURE 16-31: PIC16HV610/616 I 400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 350 (-40°C to 125°C) 300 250 200 150 100 2 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 COMPARATOR (BOTH ON) vs (V) DD WDT vs (V) DD BOR vs ...
Page 186
... Typical: Statistical Mean @25°C 400 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 350 300 250 200 150 100 DS41288F-page 186 CV (LOW RANGE) vs REF ( (HI RANGE) vs REF (V) DD T1OSC vs ( Maximum Typical 5 4 Maximum Typical 5 4 Maximum Typical 5 4 © 2009 Microchip Technology Inc. ...
Page 187
... I OVER TEMPERATURE ( 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 5.0 5.5 6.0 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 A 3.0V) DD 6.5 7.0 7.5 8.0 I (mA) OL Maximum ...
Page 188
... DS41288F-page 188 = 5.0V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 6.5 7.0 7.5 8.0 8.5 I (mA 3.0V) DD -1.5 -2.0 -2.5 I (mA) OH 9.0 9.5 10.0 Max. -40°C Typ. 25°C Min. 125°C -3.0 -3.5 -4.0 © 2009 Microchip Technology Inc. ...
Page 189
... FIGURE 16-40: TTL INPUT THRESHOLD V 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 1.3 1.1 0.9 0.7 0.5 2.0 2.5 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 = 5.0V) DD -1.5 -2.0 -2.5 -3.0 -3.5 I (mA) OH vs. V OVER TEMPERATURE ...
Page 190
... OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 V (V) DD OVER TEMPERATURE DD V Max. 125° Min. -40° Max. -40° Min. 125°C IL 4.5 5.0 5.5 4.5 5.0 5.5 © 2009 Microchip Technology Inc. ...
Page 191
... Microchip Technology Inc. PIC16F610/616/16HV610/616 OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 V (V) DD OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ ...
Page 192
... PIC16F610/616/16HV610/616 FIGURE 16-45: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 16-46: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 DS41288F-page 192 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 V (V) DD (25°C) DD 5.0 5.5 (85°C) DD 4.5 5.0 5.5 © 2009 Microchip Technology Inc. ...
Page 193
... FIGURE 16-47: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 16-48: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 4.5 V (V) DD (125°C) DD 5.0 5.5 (-40°C) DD 5.0 5.5 DS41288F-page 193 ...
Page 194
... FIGURE 16-51: SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL) 5.16 5.14 5.12 5.1 5.08 5.06 5.04 5.02 5 4.98 4. DS41288F-page 194 Temp ( Temp ( Input Current (mA) 2. 5.5V 100 120 140 2. 5.5V 100 120 140 -40°C 25°C 85°C 125° © 2009 Microchip Technology Inc. ...
Page 195
... FIGURE 16-53: COMPARATOR RESPONSE TIME (RISING EDGE) 1000 900 800 700 Vcm = (V - 1.5V)/2 Note: 600 DD V+ input = Vcm V- input = Transition from Vcm + 100mV to Vcm - 20mV 500 400 300 200 100 0 2.0 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Temp (C) 2.5 4 100 ...
Page 196
... FIGURE 16-55: WDT TIME-OUT PERIOD vs 1.5 2 DS41288F-page 196 - 100 2.5 4.0 V (V) DD OVER TEMPERATURE DD 2 (V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 5.5 125°C 85°C 25°C -40°C 4.5 5 5.5 6 © 2009 Microchip Technology Inc. ...
Page 197
... Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Example PIC16F616 e -I/P 0610017 Example PIC16F616-E 0610017 Example XXXX/ST 0610 Example 16F616 -I/ML 0610017 3 ...
Page 198
... PIC16F610/616/16HV610/616 17.2 Package Details The following sections give the technical details of the packages. DS41288F-page 198 © 2009 Microchip Technology Inc. ...
Page 199
... Microchip Technology Inc. PIC16F610/616/16HV610/616 φ α β DS41288F-page 199 ...
Page 200
... PIC16F610/616/16HV610/616 DS41288F-page 200 © 2009 Microchip Technology Inc. ...