PIC12F609-I/SN Microchip Technology, PIC12F609-I/SN Datasheet - Page 16

• Manufacturer Part Number: PIC12F609-I/SN
• Description: IC PIC MCU FLASH 1KX14 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F609-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS-232 / USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F609/615/12HV609/615
TABLE 2-4:
DS41302A-page 14
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
Addr
1:
2:
3:
4:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCTUNE
PR2
APFCON
WPU
IOC
ADRESL
ANSEL
Name
(2)
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
TRISIO3 always reads as ‘1’ since it is an input only pin.
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PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Module Period Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
GPPU
IRP
Bit 7
GIE
—
—
—
—
—
—
—
—
—
(1)
INTEDG
ADCS2
RP1
ADIE
Bit 6
PEIE
—
—
—
—
—
—
—
(1)
TRISIO5
CCP1IE
ADCS1
WPU5
T0CS
IOC5
Bit 5
T0IE
RP0
—
—
—
—
TRISIO4
T1GSEL
ADCS0
Preliminary
WPU4
T0SE
TUN4
IOC4
Bit 4
INTE
TO
—
—
Write Buffer for upper 5 bits of Program Counter
TRISIO3
TUN3
ANS3
GPIE
CMIE
IOC3
Bit 3
PSA
PD
—
—
—
(4)
TRISIO2
WPU2
TUN2
ANS2
IOC2
Bit 2
T0IF
PS2
—
—
—
Z
TRISIO1
P1BSEL
TMR2IE
WPU1
TUN1
ANS1
INTF
IOC1
Bit 1
POR
PS1
DC
© 2006 Microchip Technology Inc.
TRISIO0
P1ASEL
TMR1IE
GPIF
WPU0
TUN0
ANS0
IOC0
Bit 0
BOR
PS0
C
(3)
xxxx xxxx 22, 101
1111 1111 16, 101
0000 0000 22, 101
0001 1xxx 15, 101
xxxx xxxx 22, 101
--11 1111 31, 101
---0 0000 22, 101
0000 0000 17, 101
-00- 0-00 18, 101
---- --qq 20, 101
---0 0000 29, 101
1111 1111 51, 101
---0 --00 18, 101
--11 -111 34, 101
--00 0000 34, 101
xxxx xxxx 71, 101
-000 1111 33, 101
POR, BOR
Value on
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