PIC12F609-I/SN Microchip Technology, PIC12F609-I/SN Datasheet
PIC12F609-I/SN
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PIC12F609-I/SN Summary of contents
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... Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2006 Microchip Technology Inc. PIC12F609/HV609 PIC12F615/HV615 Data Sheet 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers Preliminary DS41302A ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Factory calibrated to ±1%, typical - Software selectable frequency: 4 MHz or 8 MHz • Power-Saving Sleep mode • Voltage range: - PIC12F609/615: 2.0V to 5.5V - PIC12HV609/615: 2.0V to user defined maximum (see note) • Industrial and Extended Temperature range • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • ...
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... PIC12F609/615/12HV609/615 Program Memory Device Flash (words) PIC12F609 1024 PIC12HV609 1024 PIC12F615 1024 PIC12HV615 1024 8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, TSSOP, DFN) GP5/T1CKI/OSC1/CLKIN GP4/CIN1-/T1G/OSC2/CLKOUT GP3/MCLR/V TABLE 1: PIC12F609/HV609 PIN SUMMARY ( I/O Pin Comparators GP0 7 CIN+ GP1 6 CIN0- GP2 5 COUT (1) GP3 4 — GP4 ...
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... CIN1- GP5 2 — — — 1 — — — 8 — — * Alternate pin function. Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 GP0/AN0/CIN+/P1B/ICSPDAT 2 7 PIC12F615/ HV615 GP1/AN1/CIN0-/ GP2/AN2/T0CKI/INT/COUT/CCP1/P1A PDIP, SOIC, TSSOP, DFN Timer ...
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... PIC12F609/615/12HV609/615 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 9 3.0 Oscillator Module........................................................................................................................................................................ 25 4.0 I/O Ports ..................................................................................................................................................................................... 31 5.0 Timer0 Module ........................................................................................................................................................................... 41 6.0 Timer1 Module with Gate Control............................................................................................................................................... 45 7.0 Timer2 Module (PIC12F615/HV615 only) .................................................................................................................................. 51 8.0 Comparator Module.................................................................................................................................................................... 53 9.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/HV615 only) ....................................................................................... 65 10.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/HV615 only)........................ 75 11 ...
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... Block T1G T1CKI Timer0 T0CKI © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Block Diagrams and pinout descriptions of the devices are as follows: • PIC12F609/HV609 (Figure 1-1, Table 1-1) • PIC12F615/HV615 (Figure 1-2, Table 1-2) INT 13 Data Bus Program Counter RAM 8-Level Stack 64 Bytes ...
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... PIC12F609/615/12HV609/615 FIGURE 1-2: PIC12F615/HV615 BLOCK DIAGRAM Configuration Flash Program Memory Program 14 Bus Instruction Reg Instruction Decode & Control OSC1/CLKIN Timing Generation OSC2/CLKOUT Internal Oscillator T1G* Block T1G T1CKI Timer0 T0CKI Analog-To-Digital Converter * Alternate pin function. DS41302A-page 6 INT 13 Data Bus Program Counter ...
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... TABLE 1-1: PIC12F609/HV609 PINOUT DESCRIPTION Name Function GP0/CIN+/ICSPDAT GP0 CIN+ ICSPDAT GP1/CIN0-/ICSPCLK GP1 CIN0- ICSPCLK GP2/T0CKI/INT/COUT GP2 T0CKI INT COUT GP3/MCLR/V GP3 PP MCLR V PP GP4/CIN1-/T1G/OSC2/ GP4 CLKOUT CIN1- T1G OSC2 CLKOUT GP5/T1CKI/OSC1/CLKIN GP5 T1CKI OSC1 CLKIN Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL © ...
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... PIC12F609/615/12HV609/615 TABLE 1-2: PIC12F615/HV615 PINOUT DESCRIPTION Name Function GP0/AN0/CIN+/P1B/ICSPDAT ICSPDAT GP1/AN1/CIN0-/V /ICSPCLK REF ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1/ P1A GP3/T1G*/MCLR/V PP GP4/AN3/CIN1-/T1G/P1B*/OSC2/ CLKOUT GP5/T1CKI/P1A*/OSC1/CLKIN Alternate pin function. Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL DS41302A-page 8 Input ...
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... MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC12F609/615/12HV609/615 has a 13-bit pro- gram counter capable of addressing pro- gram memory space. Only the first (0000h- 03FFh) for the PIC12F609/615/12HV609/615 is physi- cally implemented. Accessing a location above these boundaries will cause a wraparound within the first space ...
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... PIC12F609/615/12HV609/615 FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F609/HV609 File Address (1) Indirect Addr. Indirect Addr. 00h TMR0 OPTION_REG 01h PCL 02h PCL STATUS STATUS 03h FSR FSR 04h GPIO TRISIO 05h 06h 07h 08h 09h PCLATH PCLATH 0Ah INTCON INTCON 0Bh PIR1 ...
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... TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter’s (PC) Least Significant Byte ...
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... PIC12F609/615/12HV609/615 TABLE 2-2: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter’s (PC) Least Significant Byte ...
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... TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG GPPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte (1) (1) 83h ...
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... PIC12F609/615/12HV609/615 TABLE 2-4: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG GPPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte (1) (1) ...
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... Status bits, see the Section 13.0 “Instruction Set Summary”. Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC12F609/615/ 12HV609/615 and should be maintained as clear. Use of these bits is not recom- mended, since this may affect upward compatibility with future products ...
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... PIC12F609/615/12HV609/615 2.2.2.2 OPTION Register The OPTION register is a readable and writable regis- ter, which contains various control bits to configure: • Timer0/WDT prescaler • External GP2/INT interrupt • Timer0 • Weak pull-ups on GPIO REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 GPPU ...
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... T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
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... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’. DS41302A-page 18 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...
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... Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software Timer1 has not overflowed Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note: Interrupt flag bits are set when an interrupt ...
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... PIC12F609/615/12HV609/615 2.2.2.6 PCON Register The Power Control (PCON) register (see Table 11-2) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the software enable of the BOR ...
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... P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT bit 0 P1ASEL: P1A Output Pin Select bit 1 = P1A function is on GP5/T1CKI/P1A 0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A Note 1: PIC12F615/HV615 only. 2: Alternate pin function. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 (1) R/W-0 U-0 U-0 T1GSEL — — Unimplemented bit, read as ‘0’ ...
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... Table Read” (DS00556). DS41302A-page 22 2.3.2 STACK The PIC12F609/615/12HV609/615 Family has an 8- level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... FIGURE 2-5: DIRECT/INDIRECT ADDRESSING PIC12F609/615/12HV609/615 Direct Addressing (1) RP1 RP0 6 From Opcode Bank Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. 2: Accesses in this area are mirrored back into Bank 0 and Bank 1. ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 24 Preliminary © 2006 Microchip Technology Inc. ...
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... External Oscillator OSC2 Sleep OSC1 Internal Oscillator INTOSC 8 MHz © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...
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... PIC12F609/615/12HV609/615 3.2 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator mod- ules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. ...
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... The value of R varies with the Oscillator mode F selected (typically between 2 M © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. ...
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... PIC12F609/615/12HV609/615 3.3.4 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO mode, the RC circuit connects to OSC1. ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 11-1) for operation of all register bits. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 30 Preliminary © 2006 Microchip Technology Inc. ...
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... TRISIO<3> always reads ‘1’. 2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 port pins are read, this value is modified and then written to the PORT data latch. GP3 reads ‘0’ when MCLRE = 1. The TRISIO register controls the direction of the GPIO pins, even when they are being used as analog inputs ...
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... PIC12F609/615/12HV609/615 4.2 Additional Pin Functions Every GPIO pin on the PIC12F609/615/12HV609/615 has an interrupt-on-change option and a weak pull-up option. The next three sections describe these functions. 4.2.1 ANSEL REGISTER The ANSEL register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as ‘ ...
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... REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER (PIC12F609/HV609) U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 Unimplemented: Read as ‘0’ bit 3 ANS3: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. ...
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... PIC12F609/615/12HV609/615 REGISTER 4-5: WPU: WEAK PULL-UP GPIO REGISTER U-0 U-0 R/W-1 — — WPU5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled ...
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... Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC12F615/HV615 only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 4.2.4.2 Figure 4-1 shows the diagram for this pin. The GP1 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • ...
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... PIC12F609/615/12HV609/615 (1) 4.2.4.3 GP2/AN2 /T0CKI/INT/COUT/CCP1 (1) P1A Figure 4-2 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: • a general purpose I/O (1) • an analog input for the ADC • the clock input for TMR0 • an external edge triggered interrupt • ...
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... BLOCK DIAGRAM OF GP3 Data Bus RD TRISIO RD GPIO WR IOC RD IOC ( Interrupt-on- Change R Write ‘0’ to GBIF Note 1: Set has priority over Reset © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 PP (1, 2) MCLRE Reset From other GP<5:4, 2:0> pins Preliminary V DD Weak MCLRE Input Pin ...
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... PIC12F609/615/12HV609/615 (1) 4.2.4.5 GP4/AN3 /CIN1-/T1G/ (1, 2) P1B /OSC2/CLKOUT Figure 4-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: • a general purpose I/O (1, 2) • an analog input for the ADC • Comparator inverting input • a Timer1 gate (count enable) ...
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... FIGURE 4-5: BLOCK DIAGRAM OF GP5 ( Interrupt-on- Change R Write ‘0’ to GBIF Note 1: Timer1 LP Oscillator enabled. 2: Set has priority over Reset. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note 1: Alternate pin function. 2: PIC12F615/HV615 only. INTOSC Mode Data Bus WPU GPPU ...
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... PIC12F609/615/12HV609/615 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Name Bit 7 Bit 6 Bit 5 (1) ANSEL — ADCS2 ADCS1 CMCON0 CMON COUT CMOE INTCON GIE PEIE T0IE IOC — — IOC5 OPTION_REG GPPU INTEDG T0CS GPIO — — GP5 TRISIO — — TRISIO5 WPU — ...
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... Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in the Configuration Word register. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. ...
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... PIC12F609/615/12HV609/615 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. ...
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... TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 44 Preliminary © 2006 Microchip Technology Inc. ...
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... When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 6.2 Clock Source Selection The TMR1CS bit of the T1CON register is used to select the clock source ...
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... PIC12F609/615/12HV609/615 FIGURE 6-1: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow TMR1 TMR1H Oscillator OSC1/T1CKI OSC2/T1G INTOSC Without CLKOUT T1OSCEN (4, 5) GP3/T1G Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. ...
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... The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks ...
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... PIC12F609/615/12HV609/615 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • ...
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... Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1 register Timer1 gate source. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘ ...
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... PIC12F609/615/12HV609/615 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 (1) APFCON — — — CMCON0 CMON COUT CMOE CMCON1 — — — INTCON GIE PEIE T0IE (1) (1) PIE1 — ADIE CCP1IE (1) (1) PIR1 — ADIF CCP1IF TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register ...
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... T2CKPS<1:0> © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...
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... PIC12F609/615/12HV609/615 REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler ...
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... REF MUX CV REF 1 CMV REN Note © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 than the analog voltage at V parator is a digital low level. When the analog voltage greater than the analog voltage output of the comparator is a digital high level. FIGURE 8-1:SINGLE COMPARATOR ...
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... PIC12F609/615/12HV609/615 8.2 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8-3. Since the analog input pins share their con- nection with a digital input, they have reverse biased ESD protection diodes to V and V DD input, therefore, must be between V SS input voltage deviates from this range by more than 0 ...
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... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 8.3.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CMPOL bit of the CMCON0 register ...
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... PIC12F609/615/12HV609/615 8.5 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive-or gate (see Figure 8-4 and Figure 8-5). One latch is updated with the comparator output level when the CMCON0 register is read ...
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... INTCON register is also set, the device will then execute the Interrupt Service Routine. 8.7 Effects of a Reset A device Reset forces the CMCON1 register to its Reset state. This sets the comparator and the voltage reference to the OFF state. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Preliminary DS41302A-page 57 ...
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... PIC12F609/615/12HV609/615 REGISTER 8-1: CMCON0: COMPARATOR CONTROL REGISTER 0 R/W-0 R-0 R/W-0 CMON COUT CMOE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CMON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COUT: Comparator Output bit If C1POL = 1 (inverted polarity): ...
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... Output is asynchronous Note 1: Refer to Section 6.6 “Timer1 Gate”. 2: Refer to Figure 8-2. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 8.9 Synchronizing Comparator Output to Timer1 The comparator output can be synchronized with Timer1 by setting the CMSYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source ...
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... PIC12F609/615/12HV609/615 8.10 Comparator Voltage Reference The Comparator Voltage Reference module provides an internally generated voltage reference for the com- parators. The following features are available: • Independent from Comparator operation • 16-level voltage range • Output clamped • Ratiometric with V DD • Fixed Reference (0.6) The VRCON register (Register 8-3) controls the Volt- age Reference module shown in Register 8-6 ...
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... COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CMVREN (1) CV REF To Comparators and ADC Module FixedRef To Comparators and ADC Module Note 1: Care should be taken to ensure CV Section 15.0 “Electrical Specifications” for more detail. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 16 Stages Analog MUX 15 0 (1) VR<3:0> 0.6V Fixed Voltage Reference remains within the comparator common mode input range ...
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... PIC12F609/615/12HV609/615 REGISTER 8-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 CMVREN — VRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CMVREN: Comparator Voltage Reference Enable bit circuit powered on and routed to CV REF 0 = 0.6 Volt constant reference routed to CMV bit 6 Unimplemented: Read as ‘ ...
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... Note: The black areas of the comparator output represents the uncertainty due to input offsets and response time. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Figure 8-7 shows the relationship between the analog input levels and digital output of a comparator with and without hysteresis. The output of the comparator ...
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... PIC12F609/615/12HV609/615 TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Name Bit 7 Bit 6 Bit 5 ANSEL — ADCS2 ADCS1 CMCON0 CMON COUT CMOE CMCON1 — — — INTCON GIE PEIE T0IE (1) PIE1 — ADIE CCP1IE (1) PIR1 — ADIF CCP1IF GPIO — ...
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... Figure 9-1 shows the block diagram of the ADC. FIGURE 9-1: ADC BLOCK DIAGRAM (+3 INTERNAL) GP0/AN0 GP1/AN1/V REF GP2/AN2 GP4/AN3 CV REF 0.6V Reference 1.2V Reference © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 (ADC) allows V DD VCFG = 0 V REF VCFG = 1 000 001 010 011 ...
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... PIC12F609/615/12HV609/615 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 9.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...
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... If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 9.1.5 “Interrupts” for more information. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 ) V . DEVICE OPERATING FREQUENCIES (VDD > 3.0V Device Frequency (F 20 MHz ...
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... PIC12F609/615/12HV609/615 9.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 9-4 shows the two output formats. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT ...
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... Sleep and resume in-line code execution. 2: See Section 9.3 “A/D Requirements”. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 EXAMPLE 9-1: ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and GP0 input. ; ;Conversion start & polling for completion ...
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... PIC12F609/615/12HV609/615 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 U-0 ADFM VCFG — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ADFM: A/D Conversion Result Format Select bit ...
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... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 R-x R-x R-x ADRES6 ADRES5 ADRES4 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC12F609/615/12HV609/615 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (C ) must be allowed to fully HOLD charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (R ) and the internal sampling switch (R ...
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... R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD FIGURE 9-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h 003h 002h 001h 000h REF © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 V DD Sampling Switch Rss LEAKAGE V = 0.6V T ± 500 Full-Scale Range 1 LSB ideal ...
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... PIC12F609/615/12HV609/615 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 Bit 6 Bit 5 ADCON0 ADFM VCFG — ANSEL — ADCS2 ADCS1 ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte GPIO — — GP5 INTCON GIE PEIE T0IE (1) PIE1 — ...
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... PWM mode; P1A active-high; P1B active-low 1110 = PWM mode; P1A active-low; P1B active-high 1111 = PWM mode; P1A active-low; P1B active-low © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. ...
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... PIC12F609/615/12HV609/615 10.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • Every falling edge • Every rising edge • Every 4th rising edge • ...
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... Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISIO — — TRISIO5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture. Note 1: For PIC12F615/HV615 only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 CCP1M1 INTE ...
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... PIC12F609/615/12HV609/615 10.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: • Toggle the CCP1 output. • Set the CCP1 output. • Clear the CCP1 output. ...
Page 81
... Timer2 Module Register TRISIO — — TRISIO5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Compare. Note 1: For PIC12F615/HV615 only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 CCP1M1 INTE ...
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... PIC12F609/615/12HV609/615 10.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • PR2 • T2CON • CCPR1L • CCP1CON In Pulse-Width Modulation (PWM) mode, the CCP module produces 10-bit resolution PWM output on the CCP1 pin ...
Page 83
... Timer Prescale (1, 4, 16) 16 PR2 Value 0x65 Maximum Resolution (bits) 8 © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 EQUATION 10-2: Pulse Width EQUATION 10-3: OSC Duty Cycle Ratio The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation ...
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... PIC12F609/615/12HV609/615 10.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. ...
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... Half-Bridge Note 1: Pulse Steering enables outputs in Single mode. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 The PWM outputs are multiplexed with I/O pins and are designated P1A and P1B. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. ...
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... PIC12F609/615/12HV609/615 FIGURE 10-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Signal P1M<1:0> P1A Modulated (Single Output) 00 P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active Relationships: P1B Inactive • Period = (PR2 + 1) * (TMR2 Prescale Value) OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) ...
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... Standard Half-Bridge Circuit (“Push-Pull”) Half-Bridge Output Driving a Full-Bridge Circuit P1A P1B © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. FIGURE 10-8: ...
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... PIC12F609/615/12HV609/615 10.4.2 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external cir- ...
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... From Comparator 001 000 © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state ...
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... PIC12F609/615/12HV609/615 REGISTER 10-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER U-0 U-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit shutdown event has occurred; ECCP outputs are in shutdown state ...
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... FIGURE 10-12: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) Shutdown Event ECCPASE bit PWM Activity Start of PWM Period © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 PWM Period Shutdown Shutdown Event Occurs Event Clears PWM Period Shutdown Shutdown Event Occurs Event Clears ...
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... PIC12F609/615/12HV609/615 10.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off ...
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... TRISIO5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the PWM. Note 1: For PIC12F615/HV615 only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 92 Preliminary © 2006 Microchip Technology Inc. ...
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... SPECIAL FEATURES OF THE CPU The PIC12F609/615/12HV609/615 has a host of features intended to maximize system reliability, minimize cost through elimination components, provide power-saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • ...
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... PIC12F609/615/12HV609/615 REGISTER 11-1: CONFIG: CONFIGURATION WORD REGISTER — — — bit 15 (2) IOSCFS CP MCLRE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘1’ bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits 11 = BOR enabled ...
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... Memory Pro- gramming Specification” (DS41204) and thus, does not require reprogramming. 11.3 Reset The PIC12F609/615/12HV609/615 device differenti- ates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation ...
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... For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 11.3.2 MCLR PIC12F609/615/12HV609/615 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...
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... Power-up Timer will be re-initialized. Once V rises above V BOR 64 ms Reset. 11.3.5 BOR CALIBRATION The PIC12F609/615/12HV609/615 stores the BOR Word calibration values in fuses located in the Calibration Word register (2008h). The Calibration Word register is for BOR not erased when using the specified bulk erase sequence in the “ ...
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... Then, bringing MCLR high will begin execution immediately (see Figure 11-5). This is useful for testing purposes or to synchronize more than one PIC12F609/615/ 12HV609/615 device operating in parallel. Table 11-6 shows the Reset conditions for some special registers, while Table 11-5 shows the Reset conditions for all the registers ...
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... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 T PWRT T PWRT T PWRT Preliminary T OST T OST ) DD T OST DS41302A-page 99 ...
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... PIC12F609/615/12HV609/615 TABLE 11-4: INITIALIZATION CONDITION FOR REGISTERS (PIC12F609/HV609) Power-on Register Address Reset W — xxxx xxxx INDF 00h/80h xxxx xxxx TMR0 01h xxxx xxxx PCL 02h/82h 0000 0000 STATUS 03h/83h 0001 1xxx FSR 04h/84h xxxx xxxx GPIO 05h --x0 x000 PCLATH 0Ah/8Ah ---0 0000 ...
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... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 11-6 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 MCLR Reset WDT Reset (1) Brown-out Reset uuuu uuuu ...
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... PIC12F609/615/12HV609/615 TABLE 11-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep Legend unchanged unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution ...
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... Interrupts The PIC12F609/615/12HV609/615 has 8 sources of interrupt: • External Interrupt GP2/INT • Timer0 Overflow Interrupt • GPIO Change Interrupts • Comparator Interrupt • A/D Interrupt (615 only) • Timer1 Overflow Interrupt • Timer2 Match Interrupt (615 only) • Enhanced CCP Interrupt (615 only) ...
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... PIC12F609/615/12HV609/615 11.4.2 TIMER0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. FIGURE 11-7: ...
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... ADIF CCP1IF (1) (1) PIE1 — ADIE CCP1IE Legend unknown unchanged, – = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by the interrupt module. Note 1: PIC12F615/HV615 only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 (1) (2) Interrupt Latency Inst ( — ...
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... Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC12F609/615/12HV609/615 does not require saving the PCLATH. However, if computed GOTOs are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR ...
Page 109
... OPTION_REG GPPU INTEDG T0CS CONFIG IOSCFS CP MCLRE Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 11-1 for operation of all Configuration Word register bits. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 1 0 8-bit Prescaler PSA PS<2:0> 0 PSA Bit 4 Bit 3 ...
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... PIC12F609/615/12HV609/615 11.7 Power-Down Mode (Sleep) The Power-Down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • WDT will be cleared but keeps running. • PD bit in the STATUS register is cleared. • TO bit is set. • Oscillator driver is turned off. • I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance) ...
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... ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 OST (2) T (3) Interrupt Latency Processor in ...
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... MCLR pins and frees all normally available pins to the user. A special debugging adapter allows the ICD device to be used in place of a PIC12F609/615/12HV609/615 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC12F609/615/12HV609/ 615 ICD device is held low, the In-Circuit Debugger functionality is enabled ...
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... FIGURE 12-1: VOLTAGE REGULATOR V UNREG R I SER SUPPLY I SHUNT C Feedback BYPASS Device © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 An external current limiting resistor, R between the unregulated supply, V pin, drops the difference in voltage between V and SER defined by Equation 12- EQUATION 12-1: supply current R MAX ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 112 Preliminary © 2006 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY The PIC12F609/615/12HV609/615 instruction set is highly orthogonal and is comprised of three basic cate- gories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...
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... PIC12F609/615/12HV609/615 TABLE 13-2: PIC12F609/615/12HV609/615 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW – Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ ...
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... Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 BCF Syntax: k Operands: Operation: Status Affected: Description: ...
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... PIC12F609/615/12HV609/615 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next ...
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... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 INCFSZ Syntax: Operands: Operation: Status Affected: Description: ...
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... PIC12F609/615/12HV609/615 MOVF Move f Syntax: [ label ] MOVF f,d Operands 127 d [0,1] Operation: (f) (dest) Status Affected: Z Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’ destination is W register the destination is file register ‘f’ itself useful to test a file register since Status flag Z is affected ...
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... Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 RETLW Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example: TABLE DONE RETURN Syntax: Operands: Operation: ...
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... PIC12F609/615/12HV609/615 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands 127 d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. ...
Page 123
... W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 XORWF Syntax: Operands: Operation: Status Affected: Description: f<3:0> f<3:0> Preliminary Exclusive OR W with f ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 122 Preliminary © 2006 Microchip Technology Inc. ...
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... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... PIC12F609/615/12HV609/615 14.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
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... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, connecting to the host PC via an RS-232 or high-speed USB interface ...
Page 128
... PIC12F609/615/12HV609/615 14.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
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... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 ........................................................................... -0. ...
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... PIC12F609/615/12HV609/615 FIGURE 15-1: PIC12F609/615 VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC12HV609/615 VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.0 4.5 4.0 3.5 3.0 2 ...
Page 131
... DC Characteristics: PIC12F609/615/12HV609/615-I (Industrial) PIC12F609/615/12HV609/615-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 PIC12F609/615 D001 PIC12HV609/615 D001B PIC12F609/F615 D001B PIC12HV609/615 D001C PIC12F609/615 D001C PIC12HV609/615 D001D PIC12F609/615 D001D PIC12HV609/615 D002* V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on ...
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... PIC12F609/615/12HV609/615 15.2 DC Characteristics: PIC12F609/615/12HV609/615-I (Industrial) PIC12F609/615/12HV609/615-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. (1, 2) D010 Supply Current ( D011* D012 D013* D014 D016* D017 D018 D019 * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
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... Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 -40° Min Typ† ...
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... PIC12F609/615/12HV609/615 15.4 PIC12F609/615/12HV609/615 DC Characteristics: Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020E Power-down Base (2) Current ( PIC12HV609/HV615 D021E D022E D023E D024E D025E* D026E D027E * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
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... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 PIC12F609/615/12HV609/615-I (Industrial) PIC12F609/615/12HV609/615-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...
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... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode. DS41302A-page 134 PIC12F609/615/12HV609/615-I (Industrial) PIC12F609/615/12HV609/615-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...
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... Derated Power DER * These parameters are characterized but not tested. Note current to run the chip alone without driving any load on the output pins. DD © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 +125°C Typ Units 84.6* C/W 8-pin PDIP package 163* C/W 8-pin SOIC package ...
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... PIC12F609/615/12HV609/615 15.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O Port mc MCLR Uppercase letters and their meanings Fall ...
Page 139
... AC Characteristics: PIC12F609/615/12HV609/615 (Industrial, Extended) FIGURE 15-4: CLOCK TIMING Q4 OSC1/CLKIN OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. OS01 F External CLKIN Frequency OSC (1) Oscillator Frequency ...
Page 140
... PIC12F609/615/12HV609/615 TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. OS06 T Internal Oscillator Switch WARM (3) when running OS08 INT Internal Calibrated OSC (2) INTOSC Frequency OS10* T INTOSC Oscillator Wake- IOSC ST up from Sleep Start-up Time * These parameters are characterized but not tested ...
Page 141
... These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output Includes OSC2 in CLKOUT mode. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Fetch Read Q1 Q2 OS11 OS20 ...
Page 142
... PIC12F609/615/12HV609/615 FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time (1) Internal Reset Watchdog Timer (1) Reset I/O pins Note 1: Asserted low. FIGURE 15-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) ...
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... OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices design. 3: Period of the slower clock ensure these voltage tolerances, V possible. 0.1 F and 0.01 F values in parallel are recommended. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 +125°C Min Typ† Max Units 2 — — 5 — ...
Page 144
... PIC12F609/615/12HV609/615 FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. 40 T0CKI High Pulse Width T 41 T0CKI Low Pulse Width ...
Page 145
... These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 CC01 CC02 CC03 +125°C Min No Prescaler 0 ...
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... PIC12F609/615/12HV609/615 TABLE 15-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristics No. CM01 V Input Offset Voltage OS CM02 V Input Common Mode Voltage CM CM03* C Common Mode Rejection Ratio MRR CM04* T Response Time RT CM05 Comparator Mode Change to Output Valid ...
Page 147
... REF 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Standard Operating Conditions (unless otherwise stated) Operating temperature Min Typ Max 4 ...
Page 148
... PIC12F609/615/12HV609/615 TABLE 15-12: PIC12F615/HV615 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. AD130* T A/D Clock Period AD A/D Internal RC Oscillator Period AD131 T Conversion Time CNV (not including (1) Acquisition Time) AD132* T Acquisition Time ACQ AD133* T Amplifier Settling Time ...
Page 149
... T OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 ( AD131 AD130 OLD_DATA Sampling Stopped is added before the A/D clock starts. This allows the ...
Page 150
... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 148 Preliminary © 2006 Microchip Technology Inc. ...
Page 151
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs are not available at this time. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Preliminary DS41302A-page 149 ...
Page 152
... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 150 Preliminary © 2006 Microchip Technology Inc. ...
Page 153
... Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Example XXFXXX/P e ...
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... PIC12F609/615/12HV609/615 17.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Dimension Limits Number of Pins ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Units ...
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... PIC12F609/615/12HV609/615 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width ...
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... Package may have one or more exposed tie bars at ends. 3. § Significant Characteristic 4. Package is saw singulated 5. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 EXPOSED PAD D2 ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 156 Preliminary © 2006 Microchip Technology Inc. ...
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... This is a new data sheet. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 APPENDIX B: This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX Family of devices. B.1 PIC12F675 to PIC12F609/615/ 12HV609/615 TABLE B-1: FEATURE COMPARISON Feature Max Operating Speed Max Program Memory (Words) ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 158 Preliminary © 2006 Microchip Technology Inc. ...
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... ADCON0 Register............................................................... 70 ADRESH Register (ADFM = 0) ........................................... 71 ADRESH Register (ADFM = 1) ........................................... 71 ADRESL Register (ADFM = 0)............................................ 71 ADRESL Register (ADFM = 1)............................................ 71 Analog Input Connection Considerations............................ 54 Analog-to-Digital Converter. See ADC ANSEL Register (PIC12F609/HV609) ................................ 33 ANSEL Register (PIC12F615/HV615) ................................ 33 APFCON Register............................................................... 21 Assembler MPASM Assembler................................................... 124 B Block Diagrams (CCP) Capture Mode Operation ................................. 76 ADC ...
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... PIC12F609/615/12HV609/615 Indirect Addressing ..................................................... 22 Initializing GPIO .......................................................... 31 Saving Status and W Registers in RAM ................... 106 Code Protection ................................................................ 109 Comparator ......................................................................... 53 Associated registers.................................................... 64 Control ........................................................................ 55 Gating Timer1 ............................................................. 59 Operation During Sleep .............................................. 57 Overview ..................................................................... 53 Response Time ........................................................... 55 Synchronizing COUT w/Timer1 .................................. 59 Comparator Hysteresis ....................................................... 63 Comparator Voltage Reference (CV ) REF Response Time ........................................................... 55 Comparator Voltage Reference (CV ) ............................ 60 REF Effects of a Reset ...
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... PIR1 (Peripheral Interrupt Register 1) ........................ 19 PWM1CON (Enhanced PWM Control) ....................... 91 Reset Values (PIC12F609/HV609)........................... 100 Reset Values (PIC12F615/HV615)........................... 101 Reset Values (special registers)............................... 102 Special Function Registers........................................... 9 Special Register Summary (PIC12F609/HV609) . 11, 13 Special Register Summary (PIC12F615/HV615) . 12, 14 STATUS ..................................................................... 15 T1CON ....................................................................... 49 T2CON ....................................................................... 52 Preliminary DS41302A-page 161 ...
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... PIC12F609/615/12HV609/615 TRISIO (Tri-State GPIO) ............................................. 31 VRCON (Voltage Reference Control) ......................... 62 WPU (Weak Pull-Up GPIO) ........................................ 34 Reset................................................................................... 95 Revision History ................................................................ 157 S Shoot-through Current ........................................................ 90 Sleep Power-Down Mode ................................................... 108 Wake-up.................................................................... 108 Wake-up using Interrupts .......................................... 108 Software Simulator (MPLAB SIM)..................................... 124 Special Event Trigger.......................................................... 68 Special Function Registers ................................................... 9 STATUS Register................................................................ 15 T T1CON Register ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC12F609/615/12HV609/615 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office PART NO. X /XX Device Temperature Package Range Device: PIC12F609, PIC12F609T PIC12F615, PIC12F615T V range 2.0V to 5.5V (F devices only) DD Temperature +85 C Range - +125 C Package Plastic DIP MD = 8-lead Plastic Dual Flat, No Lead (4x4x0.9mm) ...
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... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary © 2006 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-3910 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...