PIC12F609-I/SN Microchip Technology, PIC12F609-I/SN Datasheet

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PIC12F609-I/SN

Manufacturer Part Number
PIC12F609-I/SN
Description
IC PIC MCU FLASH 1KX14 8SOIC
Manufacturer
Microchip Technology
Series
PIC® 12Fr

Specifications of PIC12F609-I/SN

Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
8-SOIC (3.9mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS-232 / USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
5
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F609-I/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC12F609-I/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
5 000
Part Number:
PIC12F609-I/SN
0
PIC12F609/615/617
PIC12HV609/615
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
 2010 Microchip Technology Inc.
DS41302D

Related parts for PIC12F609-I/SN

PIC12F609-I/SN Summary of contents

Page 1

... Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.  2010 Microchip Technology Inc. PIC12F609/615/617 PIC12HV609/615 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS41302D ...

Page 2

... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Factory calibrated to ±1%, typical - Software selectable frequency: 4 MHz or 8 MHz • Power-Saving Sleep mode • Voltage Range: - PIC12F609/615/617: 2.0V to 5.5V - PIC12HV609/615: 2.0V to user defined maximum (see note) • Industrial and Extended Temperature Range • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • ...

Page 4

... Device Flash SRAM (bytes) (words) PIC12F609 1024 64 PIC12HV609 1024 64 PIC12F615 1024 64 PIC12HV615 1024 64 PIC12F617 2048 128 8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN) GP5/T1CKI/OSC1/CLKIN GP4/CIN1-/T1G/OSC2/CLKOUT GP3/MCLR/V TABLE 1: PIC12F609/HV609 PIN SUMMARY ( I/O Pin Comparators GP0 7 CIN+ GP1 6 CIN0- GP2 5 COUT (1) GP3 4 — ...

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... PIC12F609/615/617/12HV609/615 8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN) GP5/T1CKI/P1A*/OSC1/CLKIN GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT GP3/T1G*/MCLR/V * Alternate pin function. TABLE 2: PIC12F615/617/HV615 PIN SUMMARY ( Comparator I/O Pin Analog s GP0 7 AN0 CIN+ GP1 6 AN1 CIN0- GP2 5 AN2 COUT (1) GP3 4 — — GP4 3 AN3 CIN1- ...

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... PIC12F609/615/617/12HV609/615 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 7 2.0 Memory Organization ................................................................................................................................................................ 11 3.0 Flash Program Memory Self Read/Self Write Control (PIC12F617 only).................................................................................. 27 4.0 Oscillator Module ....................................................................................................................................................................... 37 5.0 I/O Port ...................................................................................................................................................................................... 43 6.0 Timer0 Module .......................................................................................................................................................................... 53 7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57 8.0 Timer2 Module (PIC12F615/617/HV615 only) .......................................................................................................................... 65 9.0 Comparator Module ................................................................................................................................................................... 67 10 ...

Page 7

... Oscillator Block T1G T1CKI Timer0 T0CKI  2010 Microchip Technology Inc. Block Diagrams and pinout descriptions of the devices are as follows: • PIC12F609/HV609 (Figure 1-1, Table 1-1) • PIC12F615/617/HV615 (Figure 1-2, Table 1-2) INT 13 Data Bus Program Counter RAM 8-Level Stack 64 Bytes ...

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... PIC12F609/615/617/12HV609/615 FIGURE 1-2: PIC12F615/617/HV615 BLOCK DIAGRAM Configuration Flash and 2K X 14** Program Memory Program 14 Bus Instruction Reg Instruction Decode & Control OSC1/CLKIN Timing Generation OSC2/CLKOUT Internal Oscillator T1G* Block T1G T1CKI Timer0 T0CKI Analog-To-Digital Converter * Alternate pin function. ** For the PIC12F617 only. ...

Page 9

... PIC12F609/615/617/12HV609/615 TABLE 1-1: PIC12F609/HV609 PINOUT DESCRIPTION Name Function GP0/CIN+/ICSPDAT GP0 CIN+ ICSPDAT GP1/CIN0-/ICSPCLK GP1 CIN0- ICSPCLK GP2/T0CKI/INT/COUT GP2 T0CKI INT COUT GP3/MCLR/V GP3 PP MCLR V PP GP4/CIN1-/T1G/OSC2/ GP4 CLKOUT CIN1- T1G OSC2 CLKOUT GP5/T1CKI/OSC1/CLKIN GP5 T1CKI OSC1 CLKIN Legend: AN=Analog input or output ST=Schmitt Trigger input with CMOS levels  ...

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... PIC12F609/615/617/12HV609/615 TABLE 1-2: PIC12F615/617/HV615 PINOUT DESCRIPTION Name Function GP0/AN0/CIN+/P1B/ICSPDAT ICSPDAT GP1/AN1/CIN0-/V /ICSPCLK REF ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1/ P1A GP3/T1G*/MCLR/V PP GP4/AN3/CIN1-/T1G/P1B*/OSC2/ CLKOUT CLKOUT GP5/T1CKI/P1A*/OSC1/CLKIN Alternate pin function. Legend: AN=Analog input or output ST=Schmitt Trigger input with CMOS levels DS41302D-page 10 Input ...

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... Accessing a location above these boundaries will cause a wrap-around within the first space for PIC12F609/615/12HV609/615 devices, and within the first space for the PIC12F617 device. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). ...

Page 12

... PIC12F609/615/617/12HV609/615 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized the PIC12F609/615/12HV609/615, and as 128 the PIC12F617. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS ...

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... PIC12F609/615/617/12HV609/615 FIGURE 2-4: DATA MEMORY MAP OF THE PIC12F615/617/HV615 File Address (1) Indirect Addr. Indirect Addr. 00h TMR0 OPTION_REG 01h PCL 02h PCL STATUS STATUS 03h FSR FSR 04h GPIO TRISIO 05h 06h 07h 08h 09h PCLATH PCLATH 0Ah INTCON INTCON 0Bh PIR1 ...

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... PIC12F609/615/617/12HV609/615 TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter’s (PC) Least Significant Byte ...

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... PIC12F609/615/617/12HV609/615 TABLE 2-2: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter’s (PC) Least Significant Byte ...

Page 16

... PIC12F609/615/617/12HV609/615 TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_RE GPPU INTEDG G 82h PCL Program Counter’s (PC) Least Significant Byte (1) (1) ...

Page 17

... PIC12F609/615/617/12HV609/615 TABLE 2-4: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG GPPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte (1) (1) ...

Page 18

... Status bits, see the Section 14.0 “Instruction Set Summary”. Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC12F609/615/617/ 12HV609/615 and should be maintained as clear. Use of these bits is not recom- mended, since this may affect upward compatibility with future products ...

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... PIC12F609/615/617/12HV609/615 2.2.2.2 OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • Timer0/WDT prescaler • External GP2/INT interrupt • Timer0 • Weak pull-ups on GPIO REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 GPPU INTEDG ...

Page 20

... PIC12F609/615/617/12HV609/615 2.2.2.3 INTCON Register The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, GPIO change and external GP2/INT pin interrupts. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 GIE ...

Page 21

... TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.  2010 Microchip Technology Inc. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...

Page 22

... Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software Timer1 has not overflowed Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’. DS41302D-page 22 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...

Page 23

... PIC12F609/615/617/12HV609/615 2.2.2.6 PCON Register The Power Control (PCON) register (see Table 12-2) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the software enable of the BOR ...

Page 24

... PIC12F609/615/617/12HV609/615 2.2.2.7 APFCON Register (PIC12F615/617/HV615 only) The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. For this device, the P1A, P1B and Timer1 Gate functions can be moved between different pins. The APFCON register bits are shown in Register 2-7. ...

Page 25

... Table Read” (DS00556).  2010 Microchip Technology Inc. 2.3.2 STACK The PIC12F609/615/617/12HV609/615 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...

Page 26

... PIC12F609/615/617/12HV609/615 FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F609/615/617/12HV609/615 Direct Addressing (1) From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figure 2-3. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. ...

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... PIC12F609/615/617/12HV609/615 3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL (FOR PIC12F617 ONLY) The Flash program memory is readable and writable during normal operation (full V range). This memory DD is not directly mapped in the register file space. Instead indirectly addressed through the Special Function Registers (see Registers 3-1 to 3-5). There are six SFRs used to read and write this memory: • ...

Page 28

... PIC12F609/615/617/12HV609/615 REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA REGISTER R/W-0 R/W-0 R/W-0 PMDATL7 PMDATL6 PMDATL5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 PMDATL<7:0>: 8 Least Significant Address bits to Write or Read from Program Memory REGISTER 3-2: PMADRL: PROGRAM MEMORY ADDRESS REGISTER ...

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... PIC12F609/615/617/12HV609/615 REGISTER 3-5: PMCON1 – PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS: 93h) U-1 U-0 U-0 — — — bit 7 bit 7 Unimplemented: Read as ‘1’ bit 6-3 Unimplemented: Read as ‘0’ bit 2 WREN: Program Memory Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM ...

Page 30

... PIC12F609/615/617/12HV609/615 3.3 Reading the Flash Program Memory To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers, and then set control bit RD (PMCON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle after to read the data. This causes the second instruction immediately following the “ ...

Page 31

... PIC12F609/615/617/12HV609/615 FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash DATA INSTR (PC) INSTR ( BSF PMCON1,RD Executed here Executed here RD bit PMDATH PMDATL Register PMRHLT  2010 Microchip Technology Inc. PMADRH,PMADRL PC+3 INSTR ( PMDATH,PMDATL INSTR ( INSTR ( NOP Executed here Executed here ...

Page 32

... PIC12F609/615/617/12HV609/615 3.4 Writing the Flash Program Memory A word of the Flash program memory may only be written to if the word unprotected segment of memory. Flash program memory must be written in four-word blocks. See Figure 3-2 and Figure 3-3 for more details. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where PMADRL< ...

Page 33

... PIC12F609/615/617/12HV609/615 FIGURE 3-2: BLOCK WRITES TO 2K FLASH PROGRAM MEMORY First word of block to be written 14 PMADRL<1:0> PMADRL<1:0> Buffer Register FIGURE 3-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION Flash ADDR INSTR INSTR ignored Flash read ( (PC) DATA BSF PMCON1,WR INSTR ( Executed here Executed here ...

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... PIC12F609/615/617/12HV609/615 An example of the complete four-word write sequence is shown in Example 3-2. The initial address is loaded into the PMADRH and PMADRL register pair; the eight words of data are loaded using indirect addressing. EXAMPLE 3-2: WRITING TO FLASH PROGRAM MEMORY ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; This write routine assumes the following: ...

Page 35

... PIC12F609/615/617/12HV609/615 TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY Name Bit 7 Bit 6 Bit 5 PMCON1 — — — PMCON2 Program Memory Control Register 2 (not a physical register) PMADRL PMADRL7 PMADRL6 PMADRL5 PMADRH — — — PMDATL PMDATL7 PMDATL6 PMDATL5 PMDATH — — PMDATH5 Legend unknown unchanged, — ...

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... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 36  2010 Microchip Technology Inc. ...

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... PIC12F609/615/617/12HV609/615 4.0 OSCILLATOR MODULE 4.1 Overview The Oscillator module has a wide variety of clock sources and selection features that allow used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the Oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits ...

Page 38

... PIC12F609/615/617/12HV609/615 4.2 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator mod- ules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. ...

Page 39

... PIC12F609/615/617/12HV609/615 4.3.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The mode selects a low, medium or high gain setting of the internal inverter- amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier ...

Page 40

... PIC12F609/615/617/12HV609/615 4.3.4 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4 ...

Page 41

... PIC12F609/615/617/12HV609/615 4.4.1.1 OSCTUNE Register The oscillator is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-1). REGISTER 4-1: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘ ...

Page 42

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 42  2010 Microchip Technology Inc. ...

Page 43

... PIC12F609/615/617/12HV609/615 5.0 I/O PORT There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. ...

Page 44

... TRISIO<3> always reads ‘1’. 2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. 5.2 Additional Pin Functions Every GPIO pin on the PIC12F609/615/617/12HV609/ 615 has an interrupt-on-change option and a weak pull- up option. The next three sections describe these functions. 5.2.1 ANSEL REGISTER The ANSEL register is used to configure the Input mode of an I/O pin to analog ...

Page 45

... PIC12F609/615/617/12HV609/615 REGISTER 5-3: ANSEL: ANALOG SELECT REGISTER (PIC12F609/HV609) U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 Unimplemented: Read as ‘0’ bit 3 ANS3: Analog Select Between Analog or Digital Function on Pin GP4 1 = Analog input ...

Page 46

... PIC12F609/615/617/12HV609/615 REGISTER 5-5: WPU: WEAK PULL-UP GPIO REGISTER U-0 U-0 R/W-1 — — WPU5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled ...

Page 47

... PIC12F609/615/617/12HV609/615 5.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. ...

Page 48

... PIC12F609/615/617/12HV609/615 (1) 5.2.4.3 GP2/AN2 /T0CKI/INT/COUT/ (1) (1) CCP1 /P1A Figure 5-2 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: • a general purpose I/O (1) • an analog input for the ADC • the clock input for TMR0 • an external edge triggered interrupt • ...

Page 49

... PIC12F609/615/617/12HV609/615 (1, 2) 5.2.4.4 GP3/T1G /MCLR/V Figure 5-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • a Timer1 gate (count enable), alternate pin • as Master Clear Reset with weak pull-up Note 1: Alternate pin function. ...

Page 50

... PIC12F609/615/617/12HV609/615 (2) 5.2.4.5 GP4/AN3 /CIN1-/T1G/ (1, 2) P1B /OSC2/CLKOUT Figure 5-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: • a general purpose I/O (2) • an analog input for the ADC • Comparator inverting input • a Timer1 gate (count enable) ...

Page 51

... PIC12F609/615/617/12HV609/615 (1, 2) 5.2.4.6 GP5/T1CKI/P1A /OSC1/CLKIN Figure 5-5 shows the diagram for this pin. The GP5 pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 clock input (1, 2) • PWM output, alternate pin • a crystal/resonator connection • a clock input ...

Page 52

... PIC12F609/615/617/12HV609/615 TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Name Bit 7 Bit 6 Bit 5 (1) ANSEL — ADCS2 ADCS1 CMCON0 CMON COUT CMOE INTCON GIE PEIE T0IE IOC — — IOC5 OPTION_REG GPPU INTEDG T0CS GPIO — — GP5 TRISIO — — TRISIO5 WPU — ...

Page 53

... PIC12F609/615/617/12HV609/615 6.0 TIMER0 MODULE The Timer0 module is an 8-bit timer/counter with the following features: • 8-bit timer/counter register (TMR0) • 8-bit prescaler (shared with Watchdog Timer) • Programmable internal or external clock source • Programmable external clock edge selection • Interrupt on overflow Figure 6 block diagram of the Timer0 module ...

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... PIC12F609/615/617/12HV609/615 6.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. ...

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... PIC12F609/615/617/12HV609/615 REGISTER 6-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register ...

Page 56

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 56  2010 Microchip Technology Inc. ...

Page 57

... PIC12F609/615/617/12HV609/615 7.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 3-bit prescaler • Optional LP oscillator • Synchronous or asynchronous operation • Timer1 gate (count enable) via comparator or T1G pin • ...

Page 58

... PIC12F609/615/617/12HV609/615 FIGURE 7-1: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow TMR1 TMR1H Oscillator OSC1/T1CKI OSC2/T1G INTOSC Without CLKOUT T1OSCEN (4, 5) GP3/T1G Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. ...

Page 59

... PIC12F609/615/617/12HV609/615 7.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples determined by the Timer1 prescaler. CY 7.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. ...

Page 60

... PIC12F609/615/617/12HV609/615 7.6 Timer1 Gate Timer1 gate source is software configurable to be the T1G pin (or the alternate T1G pin) or the output of the Comparator. This allows the device to directly time external events using T1G or analog events using the Comparator. See the CMCON1 Register (Register 9-2) for selecting the Timer1 gate source ...

Page 61

... PIC12F609/615/617/12HV609/615 7.10 ECCP Special Event Trigger (PIC12F615/617/HV615 only ECCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The ECCP module may still be configured to generate a ECCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1 ...

Page 62

... PIC12F609/615/617/12HV609/615 7.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 7-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 7-1: T1CON: TIMER 1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 (1) (2) T1GINV TMR1GE T1CKPS1 bit 7 Legend Readable bit ...

Page 63

... PIC12F609/615/617/12HV609/615 TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 (1) APFCON — — — CMCON0 CMON COUT CMOE CMCON1 — — — INTCON GIE PEIE T0IE (1) (1) PIE1 — ADIE CCP1IE (1) (1) PIR1 — ADIF CCP1IF TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register ...

Page 64

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 64  2010 Microchip Technology Inc. ...

Page 65

... PIC12F609/615/617/12HV609/615 8.0 TIMER2 MODULE (PIC12F615/617/HV615 ONLY) The Timer2 module is an 8-bit timer with the following features: • 8-bit timer register (TMR2) • 8-bit period register (PR2) • Interrupt on TMR2 match with PR2 • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) See Figure 8-1 for a block diagram of Timer2 ...

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... PIC12F609/615/617/12HV609/615 REGISTER 8-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler ...

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... PIC12F609/615/617/12HV609/615 9.0 COMPARATOR MODULE The comparator can be used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparator is a very useful mixed signal building block because it provides analog functionality independent of the program execution. ...

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... PIC12F609/615/617/12HV609/615 9.2 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 9-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes analog input, therefore, must be between V If the input voltage deviates from this range by more than 0 ...

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... PIC12F609/615/617/12HV609/615 9.3 Comparator Control The comparator has two control and Configuration registers: CMCON0 and CMCON1. The CMCON1 register is used for controlling the interaction with Timer1 and simultaneously reading the comparator output. The CMCON0 register (Register 9-1) contain the control and Status bits for the following: • ...

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... PIC12F609/615/617/12HV609/615 9.5 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive- or gate (see Figure 9-4 and Figure 9-5). One latch is updated with the comparator output level when the CMCON0 register is read ...

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... PIC12F609/615/617/12HV609/615 9.6 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 16.0 Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator ...

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... PIC12F609/615/617/12HV609/615 REGISTER 9-1: CMCON0: COMPARATOR CONTROL REGISTER 0 R/W-0 R-0 R/W-0 CMON COUT CMOE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CMON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COUT: Comparator Output bit If C1POL = 1 (inverted polarity): ...

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... PIC12F609/615/617/12HV609/615 9.8 Comparator Gating Timer1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator. This requires that Timer1 is on and gating is enabled. See Section 7.0 “Timer1 Module with Gate Control” for details ...

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... PIC12F609/615/617/12HV609/615 9.10 Comparator Voltage Reference The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: • Independent from Comparator operation • 16-level voltage range • Output clamped • Ratiometric with V DD • Fixed Reference (0.6) The VRCON register (Register 9-3) controls the Voltage Reference module shown in Register 9-6 ...

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... PIC12F609/615/617/12HV609/615 FIGURE 9-6: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CMVREN (1) CV REF To Comparators and ADC Module FixedRef To Comparators and ADC Module Note 1: Care should be taken to ensure CV Section 16.0 “Electrical Specifications” for more detail.  2010 Microchip Technology Inc. 16 Stages Analog MUX ...

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... PIC12F609/615/617/12HV609/615 REGISTER 9-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 CMVREN — VRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CMVREN: Comparator Voltage Reference Enable bit circuit powered on and routed to CV REF 0 = 0.6 Volt constant reference routed to CV bit 6 Unimplemented: Read as ‘ ...

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... PIC12F609/615/617/12HV609/615 9.11 Comparator Hysteresis Each comparator has built-in hysteresis that is user enabled by setting the CMHYS bit of the CMCON1 register. The hysteresis feature can help filter noise and reduce multiple comparator output transitions when the output is changing state. FIGURE 9-7: COMPARATOR HYSTERESIS ...

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... PIC12F609/615/617/12HV609/615 TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Name Bit 7 Bit 6 Bit 5 (1) ANSEL — ADCS2 ADCS1 CMCON0 CMON COUT CMOE CMCON1 — — — INTCON GIE PEIE T0IE (1) PIE1 — ADIE CCP1IE (1) PIR1 — ADIF ...

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... PIC12F609/615/617/12HV609/615 10.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE (PIC12F615/617/HV615 ONLY) The Analog-to-Digital Converter conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter ...

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... PIC12F609/615/617/12HV609/615 10.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 10.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...

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... PIC12F609/615/617/12HV609/615 TABLE 10-1: ADC CLOCK PERIOD (T ADC Clock Period ( ADC Clock Source ADCS<2:0> 000 OSC F /4 100 OSC F /8 001 OSC F /16 OSC 101 F /32 010 OSC F /64 110 OSC F x11 RC Legend: Shaded cells are outside of recommended range. Note 1: The F source has a typical T ...

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... PIC12F609/615/617/12HV609/615 10.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 10-4 shows the two output formats. FIGURE 10-3: 10-BIT A/D CONVERSION RESULT FORMAT ...

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... PIC12F609/615/617/12HV609/615 10.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: • Disable pin output driver (See TRIS register) • Configure pin as analog 2. Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • ...

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... PIC12F609/615/617/12HV609/615 10.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 10-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 U-0 ADFM VCFG — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ADFM: A/D Conversion Result Format Select bit ...

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... PIC12F609/615/617/12HV609/615 REGISTER 10-2: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY) R-x R-x R-x ADRES9 ADRES8 ADRES7 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result ...

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... PIC12F609/615/617/12HV609/615 10.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (C ) must be allowed to fully HOLD charge to the input channel voltage level. The Analog Input model is shown in Figure 10-4. The source impedance (R ) and the internal sampling switch (R ...

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... PIC12F609/615/617/12HV609/615 FIGURE 10-4: ANALOG INPUT MODEL ANx Rs C PIN Legend Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD FIGURE 10-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h ...

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... PIC12F609/615/617/12HV609/615 TABLE 10-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 Bit 6 Bit 5 (1) ADCON0 ADFM VCFG — (1) ANSEL — ADCS2 ADCS1 (1,2) ADRESH A/D Result Register High Byte (1,2) ADRESL A/D Result Register Low Byte GPIO — — GP5 INTCON GIE PEIE ...

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... PIC12F609/615/617/12HV609/615 11.0 ENHANCED CAPTURE/ COMPARE/PWM (WITH AUTO- SHUTDOWN AND DEAD BAND) MODULE (PIC12F615/617/ HV615 ONLY) The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event.The ...

Page 90

... PIC12F609/615/617/12HV609/615 11.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • Every falling edge • Every rising edge • Every 4th rising edge • ...

Page 91

... PIC12F609/615/617/12HV609/615 TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 CCP1CON P1M — DC1B1 CCPR1L Capture/Compare/PWM Register 1 Low Byte CCPR1H Capture/Compare/PWM Register 1 High Byte INTCON GIE PEIE T0IE (1) PIE1 — ADIE CCP1IE (1) PIR1 — ADIF CCP1IF T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC ...

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... PIC12F609/615/617/12HV609/615 11.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: • Toggle the CCP1 output. • Set the CCP1 output. • Clear the CCP1 output. ...

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... PIC12F609/615/617/12HV609/615 TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Name Bit 7 Bit 6 Bit 5 CCP1CON P1M — DC1B1 CCPR1L Capture/Compare/PWM Register 1 Low Byte CCPR1H Capture/Compare/PWM Register 1 High Byte INTCON GIE PEIE T0IE (1) PIE1 — ADIE CCP1IE (1) PIR1 — ADIF CCP1IF T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC ...

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... PIC12F609/615/617/12HV609/615 11.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • PR2 • T2CON • CCPR1L • CCP1CON In Pulse-Width Modulation (PWM) mode, the CCP module produces 10-bit resolution PWM output on the CCP1 pin ...

Page 95

... PIC12F609/615/617/12HV609/615 11.3.1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 11-1. EQUATION 11-1: PWM PERIOD       PWM Period = PR2 + 1 (TMR2 Prescale Value) When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • ...

Page 96

... PIC12F609/615/617/12HV609/615 11.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. ...

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... PIC12F609/615/617/12HV609/615 11.4 PWM (Enhanced Mode) The Enhanced PWM Mode can generate a PWM signal four different output pins with up to 10-bits of resolution. It can do this through four different PWM output modes: • Single PWM • Half-Bridge PWM To select an Enhanced PWM mode, the P1M bits of the CCP1CON register must be set appropriately ...

Page 98

... PIC12F609/615/617/12HV609/615 FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Signal P1M<1:0> P1A Modulated (Single Output) 00 P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active Relationships: P1B Inactive • Period = (PR2 + 1) * (TMR2 Prescale Value) OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) ...

Page 99

... PIC12F609/615/617/12HV609/615 11.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 11-8). This mode can be used for Half-Bridge applications, as ...

Page 100

... PIC12F609/615/617/12HV609/615 11.4.2 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high- impedance state. The external circuits ...

Page 101

... PIC12F609/615/617/12HV609/615 11.4.4 ENHANCED PWM AUTO- SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application ...

Page 102

... PIC12F609/615/617/12HV609/615 REGISTER 11-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit shutdown event has occurred; ECCP outputs are in shutdown state ...

Page 103

... PIC12F609/615/617/12HV609/615 FIGURE 11-11: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) Shutdown Event ECCPASE bit PWM Activity Start of PWM Period 11.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automati- cally restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register ...

Page 104

... PIC12F609/615/617/12HV609/615 11.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off ...

Page 105

... PIC12F609/615/617/12HV609/615 REGISTER 11-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away ...

Page 106

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 106  2010 Microchip Technology Inc. ...

Page 107

... PIC12F609/615/617/12HV609/615 12.0 SPECIAL FEATURES OF THE CPU The PIC12F609/615/617/12HV609/615 has a host of features intended to maximize system reliability, minimize cost through elimination components, provide power-saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • ...

Page 108

... PIC12F609/615/617/12HV609/615 REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER (ADDRESS: 2007h) FOR PIC12F609/615/HV609/615 ONLY U-1 U-1 U-1 U-1 R/P-1 (1) — — — — BOREN1 BOREN0 bit 13 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-10 Unimplemented: Read as ‘1’ ...

Page 109

... PIC12F609/615/617/12HV609/615 REGISTER 12-2: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) FOR PIC12F617 ONLY U-1 U-1 R/P-1 R/P-1 R/P-1 — — WRT1 WRT0 BOREN1 BOREN0 IOSCFS bit 13 bit 13-12 Unimplemented: Read as ‘1’ bit 11-10 WRT<1:0>: Flash Program Memory Self Write Enable bits ...

Page 110

... Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the Memory Programming Specification (DS41204) and thus, does not require reprogramming. 12.3 Reset The PIC12F609/615/617/12HV609/615 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) ...

Page 111

... For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 12.3.2 MCLR PIC12F609/615/617/12HV609/615 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...

Page 112

... PIC12F609/615/617/12HV609/615 12.3.4 BROWN-OUT RESET (BOR) The BOREN0 and BOREN1 bits in the Configuration Word register select one of three BOR modes. One mode has been added to allow control of the BOR enable for lower current during Sleep. By selecting BOREN<1:0> = 10, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. ...

Page 113

... Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F609/615/617/ 12HV609/615 device operating in parallel. Table 12-6 shows the Reset conditions for some special registers, while Table 12-5 shows the Reset conditions for all the registers ...

Page 114

... PIC12F609/615/617/12HV609/615 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH V ...

Page 115

... PIC12F609/615/617/12HV609/615 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (PIC12F609/HV609) Power-on Register Address Reset W — xxxx xxxx INDF 00h/80h xxxx xxxx TMR0 01h xxxx xxxx PCL 02h/82h 0000 0000 STATUS 03h/83h 0001 1xxx FSR 04h/84h xxxx xxxx GPIO 05h --x0 x000 PCLATH 0Ah/8Ah ---0 0000 ...

Page 116

... PIC12F609/615/617/12HV609/615 TABLE 12-5: INITIALIZATION CONDITION FOR REGISTERS (PIC12F615/617/HV615) Register Address Power-on Reset W — xxxx xxxx INDF 00h/80h xxxx xxxx TMR0 01h xxxx xxxx PCL 02h/82h 0000 0000 STATUS 03h/83h 0001 1xxx FSR 04h/84h xxxx xxxx GPIO 05h --x0 x000 PCLATH 0Ah/8Ah ---0 0000 ...

Page 117

... PIC12F609/615/617/12HV609/615 TABLE 12-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)(PIC12F615/617/HV615) Register Address Power-on Reset (6) PMADRH 9Bh ---- -000 (6) PMDATL 9Ch 0000 0000 (6) PMDATH 9Dh --00 0000 (1) ADRESL 9Eh xxxx xxxx ANSEL 9Fh -000 1111 Legend unchanged unknown, – = unimplemented bit, reads as ‘0’ value depends on condition. ...

Page 118

... PIC12F609/615/617/12HV609/615 12.4 Interrupts The PIC12F609/615/617/12HV609/615 has 8 sources of interrupt: • External Interrupt GP2/INT • Timer0 Overflow Interrupt • GPIO Change Interrupts • Comparator Interrupt • A/D Interrupt (PIC12F615/617/HV615 only) • Timer1 Overflow Interrupt • Timer2 Match Interrupt (PIC12F615/617/HV615 only) • Enhanced CCP Interrupt (PIC12F615/617/HV615 only) • ...

Page 119

... PIC12F609/615/617/12HV609/615 12.4.2 TIMER0 INTERRUPT An overflow (FFh  00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 6.0 “Timer0 Module” for operation of the Timer0 module. FIGURE 12-7: ...

Page 120

... PIC12F609/615/617/12HV609/615 FIGURE 12-8: INT PIN INTERRUPT TIMING OSC1 (3) CLKOUT (4) INT pin (1) INTF flag (5) (INTCON reg.) GIE bit (INTCON reg.) INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC – 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3 the same whether Inst (PC single cycle or a 2-cycle instruction. ...

Page 121

... Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC12F609/615/617/12HV609/615 does not require saving the PCLATH. However, if computed GOTOs are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR ...

Page 122

... PIC12F609/615/617/12HV609/615 12.6.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worst- case conditions (i.e Min., Temperature = Max., DD Max. WDT prescaler) it may take several seconds before a WDT time out occurs. FIGURE 12-2: WATCHDOG TIMER BLOCK DIAGRAM CLKOUT (= F /4) OSC 0 1 T0CKI ...

Page 123

... PIC12F609/615/617/12HV609/615 12.7 Power-Down Mode (Sleep) The Power-Down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • WDT will be cleared but keeps running. • PD bit in the STATUS register is cleared. • TO bit is set. • Oscillator driver is turned off. • I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance) ...

Page 124

... PIC12F609/615/617/12HV609/615 FIGURE 12-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 (4) CLKOUT INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) Instruction Flow Instruction Inst( Inst(PC) = Sleep Fetched Instruction Sleep Inst(PC – 1) Executed Note 1: XT Oscillator mode assumed 1024 T (drawing not to scale). This delay does not apply to EC, INTOSC and RC Oscillator modes. ...

Page 125

... MCLR pins and frees all normally available pins to the user. A special debugging adapter allows the ICD device to be used in place of a PIC12F609/615/617/12HV609/ 615 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC12F609/615/617/ 12HV609/615 ICD device is held low, the In-Circuit Debugger functionality is enabled ...

Page 126

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 126  2010 Microchip Technology Inc. ...

Page 127

... PIC12F609/615/617/12HV609/615 13.0 VOLTAGE REGULATOR The PIC12HV609/HV615 devices include a permanent internal 5 volt (nominal) shunt regulator in parallel with the V pin. This eliminates the need for an external DD voltage regulator in systems sourced unregulated supply. All external devices connected directly to the V pin will share the regulated supply ...

Page 128

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 128  2010 Microchip Technology Inc. ...

Page 129

... PIC12F609/615/617/12HV609/615 14.0 INSTRUCTION SET SUMMARY The PIC12F609/615/617/12HV609/615 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...

Page 130

... PIC12F609/615/617/12HV609/615 TABLE 14-2: PIC12F609/615/617/12HV609/615 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW – Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ ...

Page 131

... PIC12F609/615/617/12HV609/615 14.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW 0  k  255 Operands: (  (W) Operation: Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. ADDWF Add W and f ...

Page 132

... PIC12F609/615/617/12HV609/615 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b 0  f  127 Operands: 0  b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next ...

Page 133

... PIC12F609/615/617/12HV609/615 DECFSZ Decrement f, Skip if 0 Syntax: [ label ] DECFSZ f,d 0  f  127 Operands: d  [0,1] (  (destination); Operation: skip if result = 0 Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘ ...

Page 134

... PIC12F609/615/617/12HV609/615 MOVF Move f Syntax: [ label ] MOVF f,d 0  f  127 Operands: d  [0,1] (f)  (dest) Operation: Status Affected: Z Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’ destination is W register the destination is file register ‘f’ ...

Page 135

... PIC12F609/615/617/12HV609/615 RETFIE Return from Interrupt Syntax: [ label ] RETFIE Operands: None TOS  PC, Operation: 1  GIE Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INT- CON<7>). This is a two-cycle instruction ...

Page 136

... PIC12F609/615/617/12HV609/615 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d 0  f  127 Operands: d  [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘ ...

Page 137

... PIC12F609/615/617/12HV609/615 SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d 0 f 127 Operands: d  [0,1] (f) - (W) destination) Operation: Status Affected: C, DC, Z Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘ ...

Page 138

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 138  2010 Microchip Technology Inc. ...

Page 139

... PIC12F609/615/617/12HV609/615 15.0 DEVELOPMENT SUPPORT ® The PIC microcontrollers and dsPIC controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment ® - MPLAB IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families ...

Page 140

... PIC12F609/615/617/12HV609/615 15.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...

Page 141

... PIC12F609/615/617/12HV609/615 15.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- ® ing the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller ...

Page 142

... PIC12F609/615/617/12HV609/615 15.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchip’s Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...

Page 143

... PIC12F609/615/617/12HV609/615 16.0 ELECTRICAL SPECIFICATIONS (†) Absolute Maximum Ratings Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on V with respect to V ................................................................................................... -0.3V to +6. Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to V (1) Total power dissipation ...

Page 144

... PIC12F609/615/617/12HV609/615 FIGURE 16-1: PIC12F609/615/617 VOLTAGE-FREQUENCY GRAPH,   -40°C T +125°C A 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 16-2: PIC12HV609/615 VOLTAGE-FREQUENCY GRAPH,   -40°C T +125°C A 5.0 4 ...

Page 145

... PIC12F609/615/617/12HV609/615 16.1 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 PIC12F609/615/617 D001 PIC12HV609/615 D001B PIC12F609/615/617 D001B PIC12HV609/615 D001C PIC12F609/615/617 D001C PIC12HV609/615 D001D PIC12F609/615/617 D001D PIC12HV609/615 D002* V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR ...

Page 146

... PIC12F609/615/617/12HV609/615 16.2 DC Characteristics: PIC12F609/615/617-I (Industrial) PIC12F609/615/617-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. (1, 2) D010 Supply Current ( PIC12F609/615/617 D011* D012 D013* D014 D016* D017 D018 D019 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

Page 147

... PIC12F609/615/617/12HV609/615 16.3 DC Characteristics: PIC12HV609/615-I (Industrial) PIC12HV609/615-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. (1, 2) D010 Supply Current ( PIC12HV609/615 D011* D012 D013* D014 D016* D017 D018 D019 * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

Page 148

... PIC12F609/615/617/12HV609/615 16.4 DC Characteristics: PIC12F609/615/617 - I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020 Power-down Base (2) Current ( PIC12F609/615/617 D021 D022 D023 D024 D025* D026 D027 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

Page 149

... PIC12F609/615/617/12HV609/615 16.5 DC Characteristics: PIC12F609/615/617 - E (Extended) DC CHARACTERISTICS Param Device Characteristics No. D020E Power-down Base (2) Current ( PIC12F609/615/617 D021E D022E D023E D024E D025E* D026E D027E * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

Page 150

... PIC12F609/615/617/12HV609/615 16.6 DC Characteristics: PIC12HV609/615 - I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020 Power-down Base (2,3) Current ( PIC12HV609/615 D021 D022 D023 D024 D025* D026 D027 * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

Page 151

... PIC12F609/615/617/12HV609/615 16.7 PIC12HV609/615 DC Characteristics: Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020E Power-down Base (2,3) Current ( PIC12HV609/615 D021E D022E D023E D024E D025E* D026E D027E * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

Page 152

... This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. 6: Applies to PIC12F617 only. DS41302D-page 152 PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) Standard Operating Conditions (unless otherwise stated) -40°C  T Operating temperature -40°C  T Min Typ† ...

Page 153

... This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. 6: Applies to PIC12F617 only.  2010 Microchip Technology Inc. PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) -40°C  T Operating temperature -40°C  T Min Typ† ...

Page 154

... PIC12F609/615/617/12HV609/615 16.9 Thermal Considerations Standard Operating Conditions (unless otherwise stated) -40°C  T  +125°C Operating temperature A Param Sym Characteristic No.  TH01 Thermal Resistance JA Junction to Ambient  TH02 Thermal Resistance JC Junction to Case TH03 T Die Temperature DIE TH04 PD Power Dissipation TH05 P Internal Power Dissipation ...

Page 155

... PIC12F609/615/617/12HV609/615 16.10 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O Port mc MCLR Uppercase letters and their meanings Fall ...

Page 156

... PIC12F609/615/617/12HV609/615 16.11 AC Characteristics: PIC12F609/615/617/12HV609/615 (Industrial, Extended) FIGURE 16-4: CLOCK TIMING Q4 OSC1/CLKIN OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 16-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) -40°C  T  +125°C Operating temperature A Param Sym Characteristic No. OS01 F External CLKIN Frequency ...

Page 157

... PIC12F609/615/617/12HV609/615 TABLE 16-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) -40°C T +125°C Operating Temperature A Param Sym Characteristic No. OS06 T Internal Oscillator Switch WARM (3) when running OS07 INT Internal Calibrated OSC (2) INTOSC Frequency (4MHz) OS08 INT Internal Calibrated ...

Page 158

... PIC12F609/615/617/12HV609/615 FIGURE 16-5: CLKOUT AND I/O TIMING Cycle Write Q4 F OSC CLKOUT I/O pin (Input) I/O pin Old Value (Output) TABLE 16-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C T +125°C ...

Page 159

... PIC12F609/615/617/12HV609/615 FIGURE 16-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time (1) Internal Reset Watchdog Timer (1) Reset I/O pins Note 1: Asserted low. FIGURE 16-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) ...

Page 160

... PIC12F609/615/617/12HV609/615 TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) -40°C T Operating Temperature A Param Sym Characteristic No MCLR Pulse Width (low) MC 31* T Watchdog Timer Time-out WDT Period (No Prescaler Oscillation Start-up Timer ...

Page 161

... PIC12F609/615/617/12HV609/615 FIGURE 16-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 16-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) -40°C T +125°C Operating Temperature A Param Sym Characteristic No. 40 T0CKI High Pulse Width ...

Page 162

... PIC12F609/615/617/12HV609/615 FIGURE 16-9: PIC12F615/617/HV615 CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) Note: Refer to Figure 16-3 for load conditions. TABLE 16-6: PIC12F615/617/HV615 CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) -40°C T Operating Temperature A Param Sym Characteristic No. CC01* TccL CCP1 Input Low Time ...

Page 163

... PIC12F609/615/617/12HV609/615 TABLE 16-8: COMPARATOR VOLTAGE REFERENCE (CV Standard Operating Conditions (unless otherwise stated) -40°C  T Operating temperature A Param Sym Characteristics No. (2) CV01* C Step Size LSB CV02* C Absolute Accuracy ACC CV03* C Unit Resistor Value (R) R (1) CV04* C Settling Time ST * These parameters are characterized but not tested. ...

Page 164

... PIC12F609/615/617/12HV609/615 TABLE 16-11: PIC12F615/617/HV615 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) -40°C  T Operating temperature A Param Sym Characteristic No. AD01 N Resolution R AD02 E Integral Error IL AD03 E Differential Error DL AD04 E Offset Error OFF AD07 E Gain Error GN (3) AD06 V Reference Voltage REF ...

Page 165

... PIC12F609/615/617/12HV609/615 TABLE 16-12: PIC12F615/617/HV615 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) -40°C  T Operating temperature A Param Sym Characteristic No. AD130* T A/D Clock Period AD A/D Internal RC Oscillator Period AD131 T Conversion Time CNV (not including (1) Acquisition Time) AD132* T Acquisition Time ACQ AD133* T ...

Page 166

... PIC12F609/615/617/12HV609/615 FIGURE 16-11: PIC12F615/617/HV615 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 ( OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. DS41302D-page 166 ( AD131 AD130 OLD_DATA Sampling Stopped is added before the A/D clock starts ...

Page 167

... PIC12F609/615/617/12HV609/615 16.12 High Temperature Operation This section outlines the specifications for the PIC12F615 device operating in a temperature range (4) between -40°C and 150°C. The specifications (4) between -40°C and 150°C are identical to those shown in DS41288 and DS80329. Note 1: Writes are not allowed for Flash Program Memory above 125° ...

Page 168

... PIC12F609/615/617/12HV609/615 TABLE 16-14: DC CHARACTERISTICS FOR I Param Device Units No. Characteristics D010 A Supply Current ( D011 A D012 A mA D013 A D014 A mA D016 A A D017 mA D018 A D019 mA DS41302D-page 168 SPECIFICATIONS FOR PIC12F615-H (High Temp.) DD Min Typ Max V DD — 2.0 — ...

Page 169

... PIC12F609/615/617/12HV609/615 TABLE 16-15: DC CHARACTERISTICS FOR I Param Device Units No. Characteristics D020E Power Down Base A Current D021E A D022E A D023E A A D024E A D025E A D026E A D027E A TABLE 16-16: WATCHDOG TIMER SPECIFICATIONS FOR PIC12F615-H (High Temp.) Param Sym Characteristic No ...

Page 170

... PIC12F609/615/617/12HV609/615 TABLE 16-18: OSCILLATOR PARAMETERS FOR PIC12F615-H (High Temp.) Param Sym Characteristic No. OS08 INT Int. Calibrated INTOSC OSC (1) Freq. Note 1: To ensure these oscillator frequency tolerances, Vdd and Vss must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended. ...

Page 171

... PIC12F609/615/617 I 60 Typical: Statistical Mean @25°C 50 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125° FIGURE 17-2: PIC12F609/615/617 I 600 Typical: Statistical Mean @25°C 500 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 400 300 200 100  2010 Microchip Technology Inc. LP (32 kHz) vs. V ...

Page 172

... Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 800 600 400 200 FIGURE 17-5: PIC12F609/615/617 I 1200 Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 800 600 400 200 0 1 DS41302D-page 172 EC (4 MHz) vs ...

Page 173

... Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp  700 (-40°C to 125°C) 600 500 400 300 200 100 FIGURE 17-7: PIC12F609/615/617 I 1800 Typical: Statistical Mean @25°C 1600 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1400 1200 1000 800 600 400 200 0 1  ...

Page 174

... Typical: Statistical Mean @25°C 700 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 600 500 400 300 200 100 FIGURE 17-9: PIC12F609/615/617 I Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) DS41302D-page 174 EXTRC (4 MHz (20 MHz) vs ...

Page 175

... PIC12F609/615/617/12HV609/615 FIGURE 17-10: PIC12F609/615/617 I 9 Typical: Statistical Mean @25°C 8 Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3 7 (-40°C to 125° FIGURE 17-11: PIC12F609/615/617  2010 Microchip Technology Inc. BASE vs (V) DD COMPARATOR (SINGLE ON) vs Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3 ...

Page 176

... Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3 16 (-40°C to 85°C) 14 Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125° FIGURE 17-13: PIC12F609/615/617 I 20 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp (-40°C to 85°C) Extended: Mean (Worst-Case Temp (-40°C to 125° ...

Page 177

... Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp (-40°C to 85°C) 120 Extended: Mean (Worst-Case Temp (-40°C to 125°C) 100 FIGURE 17-15: PIC12F609/615/617 I 120 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp 100 (-40°C to 85°C) Extended: Mean (Worst-Case Temp (-40°C to 125°  ...

Page 178

... PIC12F609/615/617/12HV609/615 FIGURE 17-16: PIC12F609/615/617 I 25 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3 20 (-40°C to 125° FIGURE 17-17: PIC12F615/617 I 14 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3 12 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3 ...

Page 179

... PIC12F609/615/617/12HV609/615 FIGURE 17-18: PIC12HV609/615 I 450 Typical: Statistical Mean @25°C 400 Maximum: Mean (Worst-Case Temp) + 3 350 (-40°C to 125°C) 300 250 200 150 100 FIGURE 17-19: PIC12HV609/615 I 1000 Typical: Statistical Mean @25°C 900 Maximum: Mean (Worst-Case Temp) + 3 800 (-40°C to 125°C) ...

Page 180

... PIC12F609/615/617/12HV609/615 FIGURE 17-21: PIC12HV609/615 I 900 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 700 (-40°C to 125°C) 600 500 400 300 200 100 0 1 FIGURE 17-22: PIC12HV609/615 I 1400 Typical: Statistical Mean @25°C 1200 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) ...

Page 181

... PIC12F609/615/617/12HV609/615 FIGURE 17-24: PIC12HV609/615 I 2000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 1500 (-40°C to 125°C) 1000 500 0 1 FIGURE 17-25: PIC12HV609/615 I 1200 Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 800 600 400 ...

Page 182

... PIC12F609/615/617/12HV609/615 FIGURE 17-27: PIC12HV609/615 I Typical: Statistical Mean @25°C 500 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 400 300 200 100 FIGURE 17-28: PIC12HV609/615 I 400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 350 (-40°C to 125°C) 300 250 200 ...

Page 183

... PIC12F609/615/617/12HV609/615 FIGURE 17-30: PIC12HV609/615 I 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 400 (-40°C to 125°C) 300 200 100 0 1 FIGURE 17-31: PIC12HV609/615 I 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 400 (-40°C to 125°C) 300 200 ...

Page 184

... PIC12F609/615/617/12HV609/615 FIGURE 17-33: PIC12HV615 I Typical: Statistical Mean @25°C 400 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 350 300 250 200 150 100 FIGURE 17-34: V vs. I OVER TEMPERATURE ( 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) ...

Page 185

... PIC12F609/615/617/12HV609/615 FIGURE 17-35: V vs. I OVER TEMPERATURE ( 0.45 Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 5.0 5.5 6.0 FIGURE 17-36: V vs. I OVER TEMPERATURE ( 3.5 3.0 2.5 2.0 1.5 Typical: Statistical Mean @25° ...

Page 186

... PIC12F609/615/617/12HV609/615 FIGURE 17-37: V vs. I OVER TEMPERATURE ( 5.5 5.0 4.5 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 FIGURE 17-38: TTL INPUT THRESHOLD V 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-Case Temp) + 3 ...

Page 187

... PIC12F609/615/617/12HV609/615 FIGURE 17-39: SCHMITT TRIGGER INPUT THRESHOLD V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.0 2.5 2.0 1.5 1.0 0.5 2.0 2.5 FIGURE 17-40: TYPICAL HFINTOSC START-UP TIMES vs 85°C 12 25°C 10 -40°C ...

Page 188

... PIC12F609/615/617/12HV609/615 FIGURE 17-41: MAXIMUM HFINTOSC START-UP TIMES vs 85°C 25°C 10 -40° 2.0 2.5 3.0 FIGURE 17-42: MINIMUM HFINTOSC START-UP TIMES vs 85°C 6 25°C 5 -40° 2.0 2.5 3.0 DS41302D-page 188 OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 ...

Page 189

... PIC12F609/615/617/12HV609/615 FIGURE 17-43: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 17-44: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5  2010 Microchip Technology Inc. 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 V (V) DD (25°C) DD 5.0 5.5 (85°C) DD 4.5 5.0 5.5 DS41302D-page 189 ...

Page 190

... PIC12F609/615/617/12HV609/615 FIGURE 17-45: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 17-46: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 DS41302D-page 190 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 4.5 V (V) DD (125°C) DD 5.0 5.5 (-40°C) DD 5.0 5.5  2010 Microchip Technology Inc. ...

Page 191

... PIC12F609/615/617/12HV609/615 FIGURE 17-47: 0.6V REFERENCE VOLTAGE vs. TEMP (TYPICAL) 0.61 0.6 0.59 0.58 0.57 0.56 -60 -40 -20 FIGURE 17-48: 1.2V REFERENCE VOLTAGE vs. TEMP (TYPICAL) 1.26 1.25 1.24 1.23 1.22 1.21 1.2 -60 -40 -20 FIGURE 17-49: SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL) 5.16 5.14 5.12 5 ...

Page 192

... PIC12F609/615/617/12HV609/615 FIGURE 17-50: SHUNT REGULATOR VOLTAGE vs. TEMP (TYPICAL) 5.16 5.14 5.12 5.1 5.08 5.06 5.04 5.02 5 4.98 4.96 -60 -40 -20 FIGURE 17-51: COMPARATOR RESPONSE TIME (RISING EDGE) 1000 900 800 700 1.5V)/2 Note: 600 input = input = Transition from V 500 400 300 200 ...

Page 193

... PIC12F609/615/617/12HV609/615 FIGURE 17-52: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 800 700 600 Note 1.5V)/ input = V CM 500 V- input = Transition from V 400 300 200 100 0 2.0 FIGURE 17-53: WDT TIME-OUT PERIOD vs 1.5 2  2010 Microchip Technology Inc. - 100mV 2.5 4.0 V (V) ...

Page 194

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 194  2010 Microchip Technology Inc. ...

Page 195

... SOIC (.150”) XXXXXXXX XXXXYYWW NNN 8-Lead MSOP XXXXXX YWWNNN 8-Lead DFN (3x3 mm) XXXX YYWW NNN 8-Lead DFN (4x4 mm) (for PIC12F609/615/HV609/615 XXXXXX XXXXXX YYWW NNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘ ...

Page 196

... PIC12F609/615/617/12HV609/615 18.2 Package Details The following sections give the technical details of the packages. DS41302D-page 196  2010 Microchip Technology Inc. ...

Page 197

... PIC12F609/615/617/12HV609/615  2010 Microchip Technology Inc. α φ β DS41302D-page 197 ...

Page 198

... PIC12F609/615/617/12HV609/615 DS41302D-page 198  2010 Microchip Technology Inc. ...

Page 199

... PIC12F609/615/617/12HV609/615  2010 Microchip Technology Inc. I φ DS41302D-page 199 ...

Page 200

... PIC12F609/615/617/12HV609/615 DS41302D-page 200  2010 Microchip Technology Inc. ...

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