pcf8593 NXP Semiconductors, pcf8593 Datasheet - Page 14

• Manufacturer Part Number: pcf8593
• Description: Low Power Clock/calendar
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.10
A 32.768 kHz quartz crystal has to be connected to OSCI
(pin 1) and OSCO (pin 2). A trimmer capacitor between
OSCI and V
Chapter 14, Section 14.1). A 100 Hz clock signal is derived
from the quartz oscillator for the clock counters.
In the 50 Hz clock mode or event-counter mode the
oscillator is disabled and the oscillator input is switched to
a high-impedance state. This allows the user to feed the
50 Hz reference frequency or an external high-speed
event signal into the input OSCI.
7.10.1
When designing the printed-circuit board layout, keep the
oscillator components as close to the IC package as
possible, and keep all other signal lines as far away as
possible. In applications involving tight packing of
components, shielding of the oscillator may be necessary.
AC coupling of extraneous signals can introduce oscillator
inaccuracy.
7.11
Note that immediately following power-on, all internal
registers are undefined and, following a RESET pulse on
pin 3, must be defined via software. Attention should be
paid to the possibility that the device may be initially in
event-counter mode, in which event the oscillator will not
operate. Over-ride can be achieved via software.
Reset is accomplished by applying an external RESET
pulse (active LOW) at pin 3. When reset occurs only the
I
all clock counters are not affected by RESET. RESET
must return HIGH during device operation.
1997 Mar 25
2
C-bus interface is reset. The control/status register and
Low power clock/calendar
Oscillator and divider
Initialization (see Fig.12)
D
ESIGNING
DD
is used for tuning the oscillator (see
14
An RC combination can also be utilized to provide a
power-on RESET signal at pin 3. In this event, the values
of the RC must fulfil the following relationship to guarantee
power-on reset (see Fig.12).
RESET input must be 0.3V
(or higher).
It is recommended to set the stop counting flag of the
control/status register before loading the actual time into
the counters. Loading of illegal states may lead to a
temporary clock malfunction.
handbook, halfpage
To avoid overload of the internal diode by falling V
diode should be added in parallel to R
must be evaluated with the actual V
value will be V
reset
input
DD
C R
R R
rise-time dependent.
V DD
Fig.12 RC reset.
3
RESET
DD
PCF8593
DD
when V
V DD
R
of the application, as their
if C
8
MBD819
R
Product specification
0.2 F. Note that RC
DD
PCF8593
DD
reaches V
, an external
DDmin