pcf8593 NXP Semiconductors, pcf8593 Datasheet - Page 17

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pcf8593

Manufacturer Part Number
pcf8593
Description
Low Power Clock/calendar
Manufacturer
NXP Semiconductors
Datasheet

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9
9.1
Before any data is transmitted on the I
always carried out with the first byte transmitted after the start procedure.
The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal,
but the data signal SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.17.
9.2
The I
1997 Mar 25
handbook, full pagewidth
Low power clock/calendar
I
2
2
C-BUS PROTOCOL
C-bus configuration for the different PCF8593 READ and WRITE cycles is shown in Figs 18, 19 and 20.
Addressing
Clock/calendar READ/WRITE cycles
S
SLAVE ADDRESS
Fig.18 Master transmits to slave receiver (WRITE) mode.
handbook, halfpage
2
C-bus, the device which should respond is addressed first. The addressing is
acknowledgement
R/W
from slave
0 A
1
group 1
0
Fig.17 Slave address.
WORD ADDRESS
1
0
17
0
acknowledgement
group 2
0
from slave
A
1 R/W
MBD821
n bytes
DATA
memory word address
auto increment
acknowledgement
from slave
A
MBD822
P
Product specification
PCF8593

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