pcf8593 NXP Semiconductors, pcf8593 Datasheet - Page 15

• Manufacturer Part Number: pcf8593
• Description: Low Power Clock/calendar
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8
The I
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data
transfer may be initiated only when the bus is not busy.
8.1
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as a control signal.
8.2
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
1997 Mar 25
Low power clock/calendar
CHARACTERISTICS OF THE I
2
C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data
Bit transfer (see Fig.13)
Start and stop conditions (see Fig.14)
SDA
SCL
START condition
SDA
SCL
S
2
Fig.14 Definition of start and stop conditions.
C-BUS
data valid
data line
Fig.13 Bit transfer.
stable;
15
allowed
change
of data
STOP condition
P
MBC621
MBC622
SDA
SCL
Product specification
PCF8593