ICS1893 Integrated Circuit Systems, ICS1893 Datasheet
ICS1893
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ICS1893 Summary of contents
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... (CSMA/CD) Ethernet standards. The ICS1893 architecture is based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch applications. ...
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... ICS1893 Data Sheet - Release Section Revision History ............................................................................................................................. 9 Chapter 1 Abbreviations and Acronyms ......................................................................................... 11 Chapter 2 Conventions and Nomenclature..................................................................................... 13 Chapter 3 ICS1893 Enhanced Features ........................................................................................... 15 Chapter 4 Overview of the ICS1893.................................................................................................. 17 4.1 100Base-TX Operation .......................................................................................... 18 4.2 10Base-T Operation ............................................................................................... 18 Chapter 5 Operating Modes Overview............................................................................................. 19 5.1 Reset Operations ................................................................................................... 20 5.1.1 General Reset Operations ..................................................................................... 20 5.1.2 Specific Reset Operations ..................................................................................... 21 5.2 Power-Down Operations ........................................................................................ 22 5 ...
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... Operation: Twisted-Pair Receiver ......................................................... 55 7.5.13 10Base-T Operation: Auto Polarity Correction ....................................................... 55 7.5.14 10Base-T Operation: Isolation Transformer ........................................................... 55 7.6 Functional Block: Management Interface ............................................................... 56 7.6.1 Management Register Set Summary ..................................................................... 56 7.6.2 Management Frame Structure ............................................................................... 56 ICS1893 Rev C 6/6/00 Table of Contents Title Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 3 Table of Contents Page June, 2000 ...
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... ICS1893 Data Sheet - Release Section Chapter 8 Management Register Set ............................................................................................... 59 8.1 Introduction to Management Register Set ............................................................. 60 8.1.1 Management Register Set Outline ......................................................................... 60 8.1.2 Management Register Bit Access .......................................................................... 61 8.1.3 Management Register Bit Default Values .............................................................. 61 8.1.4 Management Register Bit Special Functions ......................................................... 62 8.2 Register 0: Control Register ................................................................................... 63 8.2.1 Reset (bit 0.15) ...................................................................................................... 63 8.2.2 Loopback Enable (bit 0.14) .................................................................................... 64 8.2.3 Data Rate Select (bit 0.13) ..................................................................................... 64 8 ...
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... Register 8: Auto-Negotiation Next Page Link Partner Ability Register ................... 86 8.10.1 Next Page (bit 8.15) ............................................................................................... 87 8.10.2 IEEE Reserved Bit (bit 8.14) .................................................................................. 87 8.10.3 Message Page (bit 8.13) ........................................................................................ 87 8.10.4 Acknowledge 2 (bit 8.12) ....................................................................................... 87 8.10.5 Message Code Field / Unformatted Code Field (bits 8.10:0) ................................. 87 ICS1893 Rev C 6/6/00 Table of Contents Title Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 5 Table of Contents Page June, 2000 ...
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... ICS1893 Data Sheet - Release Section 8.11 Register 16: Extended Control Register ................................................................ 88 8.11.1 Command Override Write Enable (bit 16.15) ......................................................... 89 8.11.2 ICS Reserved (bits 16.14:11) ................................................................................. 89 8.11.3 PHY Address (bits 16.10:6) ................................................................................... 89 8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) ..................................................... 89 8.11.5 ICS Reserved (bit 16.4) ......................................................................................... 89 8.11.6 NRZ/NRZI Encoding (bit 16.3) ............................................................................... 89 8.11.7 Invalid Error Code Test (bit 16.2) ........................................................................... 90 8.11.8 ICS Reserved (bit 16.1) ......................................................................................... 90 8.11.9 Stream Cipher Disable (bit 16.0) ............................................................................ 90 8 ...
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... Automatic 100Base-TX Power-Down (bit 19.0) ................................................... 102 Chapter 9 Pin Diagram, Listings, and Descriptions ..................................................................... 103 9.1 ICS1893 Pin Diagram .......................................................................................... 103 9.2 ICS1893 Pin Listings ............................................................................................ 104 9.3 ICS1893 Pin Descriptions .................................................................................... 105 9.3.1 Transformer Interface Pins .................................................................................. 105 9.3.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins .......................... 106 9.3.3 Configuration Pins ................................................................................................ 110 9.3.4 MAC/Repeater Interface Pins .............................................................................. 112 9 ...
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... Jabber Timing ..................................................................................... 146 10.5.21 10Base-T: Normal Link Pulse Timing .................................................................. 147 10.5.22 Auto-Negotiation Fast Link Pulse Timing ............................................................. 148 Chapter 11 Physical Dimensions of ICS1893 Package................................................................ 149 Chapter 12 Ordering Information ................................................................................................... 151 ICS1893 Rev C 6/6/00 Table of Contents Title Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. ...
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... Table 10-28. Changes to table values. – Table 10-29. Changes to table values. – Chapter 11, “ Physical Dimensions of ICS1893 Package” ICS1893 Rev C 6/6/00 . Change to text in 1(a). . New paragraph. (Subsequent paragraphs reflect . ICS1893 pin names have changes. . Changes to text in bullets. Copyright © 2000, Integrated Circuit Systems, Inc. ...
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... Section 10.3, “ Recommended Component Values” – A new figure, Figure Change Bars Change bars on subsequent ICS1893 data sheets indicate new documents posted to the web. (Change bars within a new version of a document also indicates changes to the document.) Sample change bar – ICS1893 Rev C 6/6/00 text changes ...
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... Multi-Level Transition Encoding (3 Levels) N/A Not Applicable NLP Normal Link Pulse No. Number NRZ Not Return to Zero NRZI Not Return to Zero, Invert on one OSI Open Systems Interconnection ICS1893 Rev C 6/6/00 Interpretation Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 11 Chapter 1 Abbreviations and Acronyms June, 2000 ...
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... Acronym OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893 is a physical-layer device, also referred ‘ PHY’ or ‘ PHYceiver’ . (The ICS1890 is also a physical-layer device.) PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ...
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... A pin name that includes a forward slash ‘ /’ multi-function, configuration pin. These pins provide the ability to select between two ICS1893 functions. The name provided: – Before the ‘ /’ indicates the pin name and function when the signal level on the pin is logic zero. – ...
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... The terms ‘ cleared’ , ‘ inactive’ , and ‘ de-asserted’ are synonymous. They do not necessarily infer logic zero. In reference to the ICS1893, the term ‘ Twisted-Pair Receiver’ refers to the set of Twisted-Pair Receive output pins (TP_RXP and TP_RXN). In reference to the ICS1893, the term ‘ Twisted-Pair Transmitter’ refers to the set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN). Copyright © ...
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... The ICS1890 Frequency-Locked Loop (FLL) that is part of the 100Base-TX Clock and Data Recovery circuitry is replaced with a digital FLL in the ICS1893, also resulting in lower jitter and improved stability. 4. The ICS1893 transmit circuits are improved in contrast to the ICS1890, resulting in a decrease in the magnitude of the 10Base-T harmonic content generated during transmission. (See ISO/IEC 8802-3: 1993 clause 8.3.1.3.) 5 ...
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... ICS1893 Data Sheet - Release Table 3-1. Summary of Differences between ICS1890 and ICS1893 Registers Register. ICS1890 Bit(s) Function 1.6 Reserved 3.9:4 Model Number 3.3:0 Revision Number 6.2 Next Page Able 7.15:0 Not applicable (N/A) 8.15:0 N/A 9.15:0 IEEE reserved. through 15.15:0 18.15 Reserved 19.1 Reserved 20.15:0 N/A through 31.15:0 Note: 1. There are new registers and bits. For example: a ...
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... Auto-Negotiation sublayer The ICS1893 is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1893 can interface directly to the MAC and offers multiple, configurable modes of operation. Alternately, this configurable interface can be connected to a repeater, which extends the physical layer of the OSI model ...
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... Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893 encapsulates each MAC/repeater frame, including the preamble, with an SSD and an ESD. As per the ISO/IEC Standard, the ICS1893 replaces the first octet of each MAC preamble with an SSD and appends an ESD to the end of each MAC/repeater frame. ...
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... ICS1893 is to use, either its hardware pins or its register bits. When the HW/SW bit is logic zero the ICS1893 is in hardware mode. In hardware mode, the hardware pins have priority over the internal registers for establishing the configuration settings of the ICS1893 ...
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... Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition is removed 5.1.1.3 Hot Insertion As with the ICS189X products, the ICS1893 reset design supports ‘ hot insertion’ of its MII. (That is, the ICS1893 can connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the MAC/repeater.) ICS1893 Rev C 6/6/00 ...
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... Section 5.1.1.1, “ Entering Reset” Exiting Hardware Reset After the signal on the RESETn pin transitions from a low to a high state, the ICS1893 completes in 640 ns (that is REF_IN clocks) steps 1 through 5, listed in steps are completed, the Serial Management Port is ready for normal operations, but this action does not signify the end of the reset cycle ...
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... LL, LH, and LMX Management Register bits are re-initialized to their default values. • During a reset, the ICS1893 sets all of its Management Register bits to their default values. It does not maintain the state of any Management Register bit. For more information on power-down operations, see the following: • ...
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... For example, if the ICS1893 supports 100Base-TX and 10Base-T modes – but its link partner supports 100Base-TX and 100Base-T4 modes – the two devices automatically select 100Base-TX as the highest-performance common operating mode ...
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... Data conversion from both parallel-to-serial and serial-to-parallel formats • Manchester data encoding/decoding • Data transmission/reception over a twisted-pair medium In addition, in 10Base-T mode, the ICS1893 provides a variety of control and status means to assist with Link Segment management. For more information on 10Base-T, see 10Base-T Operations” . 5.7 Half-Duplex and Full-Duplex Operations The ICS1893 supports half-duplex and full-duplex operations for both 10Base-T and 100Base-TX applications ...
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... ICS1893 - Release Chapter 6 Interface Overviews The ICS1893 MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC/repeater-to-PHY interfaces: • Section 6.1, “ MII Data Interface” • Section 6.2, “ 100M Symbol Interface” ...
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... In addition, the interface also provides status and control signals to synchronize the transfers. The ICS1893 provides a full complement of the ISO/IEC-specified MII signals. Its MII has both a transmit and a receive data path to synchronously exchange 4 bits of data (that is, nibbles). • ...
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... In the 100M Symbol Interface mode, the ICS1893 continues to assert the CRS signal using its PCS logic. This action does not affect the bit delay or latency because the PCS CRS logic examines the bits received from the PMA sublayer serially ...
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... ICS1893 Data Sheet - Release Table 6-1 lists the pin mappings for the ICS1893 100M Symbol Interface mode. Table 6-1. Pin Mappings for 100M Symbol Interface Mode Default 10M / 100M MII Pin Names COL No connect. [Because the MAC/repeater sources both active and ‘ idle’ data, a PHY cannot distinguish between an active and idle transmission channel (that is PHY the transmit channel always appears active) ...
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... When the ICS1893’ s MAC/Repeater Interface is configured for 10M Serial operations, both its default MII pin names and their associated functions are redefined. For more information, see “ MAC/Repeater Interface Pins for 10M Serial Interface” ICS1893 Rev C 6/6/00 . Copyright © ...
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... ICS1893 Data Sheet - Release Table 6-2 lists the pin mappings for the ICS1893 10M Serial Interface mode. Table 6-2. Pin Mappings for 10M Serial Interface Mode Default 10M / 100M MII Pin Names COL 10COL CRS 10CRS MDC MDC MDIO MDIO RXCLK 10RCLK RXD0 ...
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... ICS1893. The ISO/IEC standard also specifies a frame structure and protocol for this interface as well as a set of Management Registers that provide the STA with access to a PHY such as the ICS1893. A Serial Management Interface is comprised of two signals: a bi-directional data pin (MDIO) along with an associated input pin for a clock (MDC) ...
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... ICS1893 twisted-pair transmitter interface. • Two 61.9 1% resistors are in series, with a 120-nH 5% inductor between them. These components form a network that connects across both the transformer and the ICS1893 TP_TXP and TP_TXN pins. • The ICS1893 supplies the power to the transformer. (No VDD connection is required.) • ...
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... F bypass capacitor. • No bypass capacitor is used with the receive transformer center tap. • A 4.7-pF capacitor must be included across the ICS1893 side of the receive transformer. Note: 1. Keep leads as short as possible. 2. Install the resistor network as close to the ICS1893 as possible. Figure 6-2. ICS1893 Receiver Twisted Pair TP_RXP 13 4 ...
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... Functionally, the RXTRI pin affects the MII receive channel in the same way as the Control Register’ s isolate bit, bit 0.10. (The isolate bit also affects the transmit data path.) The ICS1893 can tri-state these seven signals for all five types of MAC/Repeater Interface configurations, not just the MII interface. ...
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... ICS1893 - Release 6.8 Status Interface The ICS1893 LSTA pin provides a Link Status, and its LOCK pin provides a Stream Cipher Locking Status. In addition, as listed in Table results of continual link monitoring by providing signals that are intended for driving LEDs. (For the pin numbers, see Table 9 ...
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... ICS1893 Data Sheet - Release Figure 6-3 shows typical biasing and LED connections for the ICS1893. Figure 6-3. ICS1893 LED - PHY Address P4RD P3TD 64 62 REC TRANS 10K 10K This circuit decodes to PHY address = 1. Note: 1. All LED pins must be set during reset. 2. PHY address 00 tri-states the MII interface. ...
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... ICS1893 - Release Chapter 7 Functional Blocks This chapter discusses the following ICS1893 functional blocks. • Section 7.1, “ Functional Block: Media Independent Interface” • Section 7.2, “ Functional Block: Auto-Negotiation” • Section 7.3, “ Functional Block: 100Base-X PCS and PMA Sublayers” • ...
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... The Media Independent Interface (MII) consists of two primary components interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893). This MAC-PHY part of the MII consists of three subcomponents synchronous Transmit interface that includes the following signals: ...
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... The design of the ICS1893 Auto-Negotiation sublayer supports both legacy 10Base-T connections as well as new connections that have multiple technology options for the link. For example, when the ICS1893 has the auto-negotiation process enabled and it is operating with a 10Base-T remote link partner, the ICS1893 monitors the link and automatically selects the 10Base-T operating mode – ...
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... The ICS1893 obtains the data for its FLP bursts from the Auto-Negotiation Advertisement Register (Register 4). 3. Both the ICS1893 and the remote link partner substitute Fast Link Pulse (FLP) bursts in place of the Normal Link Pulses (NLPs). In each FLP burst, the ICS1893 transmits information on its technology capability through its Link Control Word, which includes link configuration and status data ...
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... Auto-Negotiation Expansion Register’ s Parallel Detection Fault bit (bit 6.4). 7.2.3 Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893 reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), 1.4, 5.13, 17.1, and 19.13. In general, the reception of a remote fault means that the remote link partner has a problem with the integrity of its receive channel ...
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... Progress Monitor” . After the Auto-Negotiation Arbitration State Machine reaches its final state (which is Auto-Negotiation Complete), only an STA read of the QuickPoll Detailed Status Register or an ICS1893 reset can alter these status bits. Any of the following situations initiates a restart of the ICS1893 Auto-Negotiation sublayer: • ...
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... STA can determine the cause of the link failure by using the outputs of the ICS1893 Auto-Negotiation Progress Monitor. The Auto-Negotiation Progress Monitor provides the STA with four status bits of data to indicate both the history and the present state of the auto-negotiation process ...
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... Note: When configured for 100M Symbol mode operations, the MAC/Repeater Interface bypasses most of the PCS. When the ICS1893 MAC/Repeater Interface is in this mode, most of its PCS Transmit and Receive modules are inactive. However, its PCS control functions (CRS and COL) remain operational ...
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... Full-duplex mode, COL is always FALSE. 7.3.3.2 PMA Transmit Module The ICS1893 PMA Transmit module accepts a serial bit stream from its PCS and converts the data into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. ...
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... PCS Receive Module The ICS1893 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA sublayer. The PCS Receive module converts the bit stream from a serial format to a parallel format and then processes the data to detect the presence of a carrier. ...
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... A Halt symbol, it sets the Halt Symbol Detected bit in its QuickPoll Detailed Status Register (bit 17.6) to logic one. Note: An STA can force the ICS1893 to transmit symbols that are typically classified as invalid, by both (1) setting the Extended Control Register’ s Transmit Invalid Codes bit (bit 16.2) to logic one and (2) asserting the associated TXER signal. For more information, see Code Test (bit 16.2)” ...
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... Baseline wander adversely affects the noise immunity of the receiver, because the ‘ baseline’ signal moves or ‘ wanders’ from its nominal DC value. The ICS1893 uses a unique technique to restore the DC component ‘ lost’ by the medium result, the design is very robust, immune to noise and independent of the data stream ...
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... The DSP-based adaptive equalizer uses a technique that compensates for a wide range of cable lengths. The optimizing parameter for the equalization process is the overall bit error rate of the ICS1893. This technique closes the loop on the entire data reception process and provides a very high overall reliability. ...
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... ICS1893 Data Sheet - Release 7.4.7 100Base-TX Operation: Auto Polarity Correction The ICS1893 can sense and then automatically correct a signal polarity that is reversed on its Twisted-Pair Receiver inputs. A signal polarity reversal occurs when the input signals on the TP_RXP and TP_RXN pins are crossed or swapped (a problem that can occur during network installation or wiring). This function is primarily a 10Base-T function, however also active during Auto-Negotiation ...
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... Twisted-Pair Receiver using a phase-locked loop (PLL). The ICS1893 then uses this recovered clock for synchronizing data transmission between itself and the MAC/repeater. Receive-clock PLL acquisitions begin with reception of the MAC Frame Preamble and continue as long as the ICS1893 is receiving data. ICS1893 Rev C 6/6/00 .). Copyright © ...
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... ICS1893 Data Sheet - Release 7.5.4 10Base-T Operation: Idle An ICS1893 transmits Normal Link Pulses (that is, 10Base-T Idles) on its MDI in the absence of data (that is, when the MAC/repeater is not requiring it to transmit any data). During this time the link is Idle, and the ICS1893 periodically transmits link pulses at a rate of one link pulse every compliance with the ISO/IEC 8802-3 standard ...
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... When a link is invalid and the Link Monitor Function detects the presence of data, the ICS1893 does not transition the link to the valid state until after the reception of the present packet is complete. ...
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... When enabled, the ICS1893 performs the SQE Test at the completion of each transmitted packet (that is, whenever its TX_EN signal transitions from asserted to de-asserted). When the ICS1893 executes its SQE Test, it asserts the COL signal to its MAC Interface for a pre-determined time duration (ISO/IEC specified). [For more information, see (SQE)” ...
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... Normal Link Pulses (NLPs). In 10Base-T mode, an ICS1893 transmits and receives NLPs when its link is in the Idle state. In 100Base-TX mode, an ICS1893 transmits and receives NLPs during Auto-Negotiation. An STA can control this feature using the 10Base-T Operations Register bit 18.3, the Auto Polarity-Inhibit bit. When this bit is logic: • ...
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... The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the exchange of configuration, control, and status data between a PHY, such as an ICS1893, and an STA. All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange data through a pre-defined register set ...
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... A valid Management Frame includes an operation code (OP) immediately following the start-of-frame delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one for writing to a management register, 01b. The ICS1893 does not respond to the codes 00b and 11b, which the ISO/IEC specification defines as invalid. ...
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... Read, (OP is 10b) the ICS1893 obtains the contents of the register identified in the REGAD field and returns this Data to the STA synchronously with its MDC signal. • Write, (OP is 01b) the ICS1893 stores the value of the Data field in the register identified in the REGAD field. If the STA attempts to: • ...
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... Section 8.12, “ Register 17: Quick Poll Detailed Status Register” • Section 8.13, “ Register 18: 10Base-T Operations Register” • Section 8.14, “ Register 19: Extended Control Register 2” ICS1893 Rev C 6/6/00 Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 59 Chapter 8 Management Register Set ...
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... Reserved by IEEE 16 through 31 Vendor-Specific (ICS) Registers Table 8-2 lists the ICS-specific registers that the ICS1893 implements. These registers enhance the performance of the ICS1893 and provide the Station Management entity (STA) with additional control and status capabilities. Table 8-2. ICS-Specific Registers Register Address 16 ...
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... Read/Write Read/Write Zero R/W0 8.1.3 Management Register Bit Default Values The tables in this chapter specify for each register bit the default value, if one exists. The ICS1893 sets all Management Register bits to their default values after a reset. ICS1893 Management Register bits. Table 8-4. Range of Possible Valid Default Values for ICS1893 Register Bits Default Condition – ...
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... STA access. The SC bits have a default value of logic zero and are triggers to begin execution of a function. When the STA writes a logic one bit, the ICS1893 begins executing the function assigned to that bit. After the ICS1893 completes executing the function, it clears the bit to indicate that the action is complete ...
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... Reserved bits. 8.2.1 Reset (bit 0.15) This bit controls the software reset function. Setting this bit to logic one initiates an ICS1893 software reset during which all Management Registers are set to their default values and all internal state machines are set to their idle state. For a detailed description of the software reset process, see “ ...
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... Auto-Negotiation sublayer. When bit 0.12 is logic: – Zero: • The ICS1893 disables the Auto-Negotiation sublayer. • The ICS1893 bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data rate and the duplex mode. – One: • The ICS1893 enables the Auto-Negotiation sublayer. ...
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... Management Interface). The default value for bit 0.10 depends upon the PHY address of • Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893 isolates itself from the MAC/Repeater Interface. • Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893 does not isolate its MAC/Repeater Interface ...
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... One, as per the ISO/IEE 8802-3 standard, clause 22.2.4.1.9, the ICS1893 enables the collision detection circuitry for the Collision Test function, even if the ICS1893 is in Loopback mode (that is, bit 0.14 is set to 1). In this case, the Collision Test function tracks the Collision Detect signal (COL) in response to the TXEN signal ...
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... As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits. 8.3.1 100Base-T4 (bit 1.15) The STA reads this bit to learn if the ICS1893 can support 100Base-T4 operations. Bit 1.15 of the ICS1893 is permanently set to logic zero, which informs an STA that the ICS1893 cannot support 100Base-T4 operations. ...
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... Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893 supports 10Base-T, half-duplex operations.) Bit 1.11 of the ICS1893 Status Register is a Command Override Write bit., which allows an STA to alter the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in Section 8.11, “ ...
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... This default value ensures that bit 1.6 is backward compatible with the ICS1890, which does not have this capability. As the means of enabling this feature, the ICS1893 implements bit 1 Command Override Write bit, instead Read-Only bit as in the ICS1890. An STA uses the bit 1.6 to enable MF Preamble Suppression in the ICS1893 ...
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... ICS1893 Data Sheet - Release 8.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893 sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ICS1893 receives the Remote Fault bit as part of the Link Code Word exchanged during the auto-negotiation process. If the ICS1893 receives a Link Code Word from its remote link partner and the Remote Fault bit is set to: • ...
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... Operation: Link Monitor” 8.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to determine if the ICS1893 detects a Jabber condition as defined in the ISO/IEC specification.The ICS1893 Jabber Detection function is controlled by the Jabber Inhibit bit in the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the ICS1893 Jabber Detection function must be enabled. When bit 18.5 is logic: • ...
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... ICS1893 Data Sheet - Release 8.4 Register 2: PHY Identifier Register Table 8-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC specification set, the PHY Identifier Registers (Registers 2 and 3) include a unique, 32-bit PHY Identifier composed from the following: • ...
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... OUI (in IEEE Std 802-1990 format) to Management Registers 2 and 3. Table 8-8. IEEE-Assigned Organizationally Unique Identifier First Octet 2.15:12 ICS1893 Rev C 6/6/00 Table 8-8 Second Octet ...
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... ICS1893 Data Sheet - Release 8.5 Register 3: PHY Identifier Register Table 8-9 lists the bits for PHY Identifier Register (Register 3), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC specification. This register stores the following: • Part of the OUI [see the text in • ...
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... ICS1893 - Release 8.5.2 Manufacturer's Model Number (bits 3.9:4) The model number for the ICS1893 is 4 (decimal stored in bit 3.9:4 as 00100b. 8.5.3 Revision Number (bits 3.3:0) Table 8-10 lists the valid ICS1893 revision numbers, which are 4-bit binary numbers stored in bits 3.3:0. Table 8-10. ICS1893 Revision Number Decimal Bits 3.3:0 ...
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... Zero, then the ICS1893 indicates to its remote link partner that these features are disabled. (Although the default value of this bit is logic zero, the ICS1893 does support the Next Page function.) • One, then the ICS1893 advertises to its remote link partner that this feature is enabled. ...
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... Word that the ICS1893 exchanges with its remote link partner. The ICS1893 sets this bit to logic one whenever it detects a problem with the link, locally. The data in this register is sent to the remote link partner to inform it of the potential problem. If the ICS1893 does not detect a link fault, it clears bit 4.13 to logic zero. Whenever the ICS1893: • ...
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... Bit 4.9 is always logic zero, indicating that the ICS1893 cannot support 100Base-T4 operations. 8.6.5.1 Technology Ability Field: Hardware Mode When the ICS1893 is operating in hardware mode (that is, the HW/SW pin is logic zero), these TAF bits are Read-Only bits. The default value of these bits depends on the signal level on the HW/SW pin and whether the Auto-Negotiation sublayer is enabled. ...
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... ICS1893 to provide these technologies. Note: 1. The ICS1893 does not alter the value of the Status Register bits based on the TAF bits in register 4, as the ISO/IEC definitions for the Status Register bits require these bits to indicate all the capabilities of the ICS1893. ...
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... During the auto-negotiation process, the ICS1893 advertises (that is, exchanges) the capability data with its remote link partner using a pre-defined Link Code Word. The value of the Link Control Word received from its remote link partner establishes the value of the bits in this register ...
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... Zero, it indicates that the remote link partner has not received the ICS1893 Link Control Word. • One, it indicates to the ICS1893 / STA that the remote link partner has acknowledged reception of the ICS1893 Link Control Word. 8.7.3 Remote Fault (bit 5.13) The ISO/IEC specification defines bit 5.13 as the Remote Fault bit. This bit is set based on the Link Control Word received from the remote link partner. When this bit is a logic: • ...
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... Writes to a reserved bit, the STA must use the default value specified in this data sheet. ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write the default value of any reserved bits during all management register write operations ...
Page 83
... Next Page bit in its Link Control Word. 8.8.4 Next Page Able (bit 6.2) Bit 6 status bit that reports the capabilities of the ICS1893 to support the Next Page features of the auto-negotiation process. The ICS1893 sets this bit to a logic one to indicate that it can support these features ...
Page 84
... ICS1893 Data Sheet - Release 8.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 8-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page Operations. This table is compliant with the ISO/IEC specification. ...
Page 85
... Written STA, the STA must use the default value specified in this data sheet. ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write the default value of any reserved bits during all management register write operations ...
Page 86
... ICS1893 Data Sheet - Release 8.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 8-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page Operations. This table is compliant with the ISO/IEC specification ...
Page 87
... Written STA, the STA must use the default value specified in this data sheet. ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write the default value of any reserved bits during all management register write operations ...
Page 88
... ICS1893 Data Sheet - Release 8.11 Register 16: Extended Control Register Table 8-16 lists the bits for the Extended Control Register, which the ICS1893 provides to allow an STA to customize the operations of the device. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
Page 89
... The PHY address is then latched into this register. (The value of each of the PHY Address bits is unaffected by a software reset.) 8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) The Stream Cipher Scrambler Test Mode bit is used to force the ICS1893 to lose LOCK, thereby requiring the Stream Cipher Scrambler to resynchronize. 8.11.5 ICS Reserved (bit 16.4) See Section 8.11.2, “ ...
Page 90
... ICS1893 Data Sheet - Release 8.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893 to transmit symbols that are typically classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC 4B/5B definition ...
Page 91
... Note: 1. For an explanation of acronyms used in 2. Most of this register’ s bits are latching high or latching low, which allows the ICS1893 to capture and save the occurrence of an event for an STA to read. (For more information on latching high and latching low bits, see Section 8.1.4.1, “ ...
Page 92
... ICS1893 Data Sheet - Release 8.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘ selected technology’ the ICS1893 is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. • Software mode, the value of this bit is determined by the Data Rate bit 0.13. ...
Page 93
... Auto-Negotiation Completed Successfully 8.12.4 100Base-TX Receive Signal Lost (bit 17.10) The 100Base-TX Receive Signal Lost bit indicates to an STA whether the ICS1893 has lost its 100Base-TX Receive Signal. If this bit is set to a logic: • Zero, it indicates the Receive Signal has remained valid since either the last read or reset of this register. ...
Page 94
... This bit has no definition in 10Base-T mode. 8.12.6 False Carrier (bit 17.8) The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893 in 100Base mode. A False Carrier occurs when the ICS1893 begins evaluating potential data on the incoming 100Base data stream, only to learn that it was not a valid /J/K/. If this bit is set to a logic: • ...
Page 95
... The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream by the ICS1893. During reception of a valid packet, the ICS1893 examines each symbol to ensure that the data being passed to the MAC/Repeater Interface is error free. If two consecutive Idles are encountered, it indicates this condition to the MAC/repeater by setting this bit ...
Page 96
... ICS1893 Data Sheet - Release 8.12.12 Jabber Detect (bit 17.2) Bit 17.2 is functionally identical to bit 1.1. The Jabber Detect bit indicates whether a jabber condition has occurred. This bit is a 10Base-T function. 8.12.13 Remote Fault (bit 17.1) Bit 17.1 is functionally identical to bit 1.4. 8.12.14 Link Status (bit 17.0) Bit 17.0 is functionally identical to bit 1.2. ICS1893 Rev C 6/6/00 Copyright © ...
Page 97
... Link Loss inhibit 18.0 Squelch inhibit 8.13.1 Remote Jabber Detect (bit 18.15) The Remote Jabber Detect bit is provided to indicate that an ICS1893 port has detected a Jabber Condition on its receive path. This bit is reset to logic zero on a read of the 10Base-T operations register. When this bit is logic: • ...
Page 98
... ICS1893 Data Sheet - Release 8.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893 has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity is: • Correct, the ICS1893 sets bit 18. logic zero. ...
Page 99
... ICS1893 - Release 8.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893 from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted- Pair Receiver inputs. • ...
Page 100
... ICS1893 Data Sheet - Release 8.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893 operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
Page 101
... Zero, the NOD/REP input pin is pulled down, which instructs the operation code to operate in Node mode. • One, the NOD/REP input pin is pulled up, which instructs the ICS1893 to operate in Repeater mode. There are two primary differences between Node mode and Repeater mode. • ...
Page 102
... Section 8.11.2, “ ICS Reserved (bits 16.14:11)” 8.14.9 Automatic 100Base-TX Power-Down (bit 19.0) The Automatic 100Base-TX Power Down bit provides an STA with the means of enabling the ICS1893 to automatically shut down 100Base-TX support functions when 10Base-T operations are being used. When this bit is set to logic: • ...
Page 103
... TP_TXP 5 TP_TXN 6 VDD 7 VDD 8 10TCSR 9 100TCSR 10 VSS 11 VSS 12 TP_RXP 13 TP_RXN 14 VDD 15 VDD 16 ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions ICS1893 Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 103 48 TXD3 47 TXD2 46 TXD1 45 TXD0 44 TXEN 43 TXCLK 42 TXER 41 RXTRI 40 VSS ...
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... ICS1893 Data Sheet - Release 9.2 ICS1893 Pin Listings Table 9-1 lists the ICS1893 pins by pin number. Table 9-1. ICS1893 Pins, by Pin Number Pin Pin Name No. 1 NOD/REP 2 10/100SEL 3 TP_CT 4 VSS 5 TP_TXP 6 TP_TXN 7 VDD 8 VDD 9 10TCSR 10 100TCSR 11 VSS 12 VSS 13 TP_RXP 14 TP_RXN 15 VDD 16 VDD ICS1893 Rev C 6/6/00 ...
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... ICS1893 - Release 9.3 ICS1893 Pin Descriptions The tables in this section list the ICS1893 pins by their functional grouping. 9.3.1 Transformer Interface Pins Table 9-2 lists the pins for the transformer interface group of pins. Table 9-2. Transformer Interface Pins Pin Pin Pin Name Number Type TP_RXN 14 Input ...
Page 106
... Note: 1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1893 exits the reset state. After sampling is complete, these pins are output pins that can drive status LEDs software reset does not affect the state of a multi-function configuration pin. During a software reset, all multi-function configuration pins are outputs ...
Page 107
... De-asserted, this state indicates the ICS1893 does not detect any collisions. – Asserted, this state indicates the ICS1893 detects collisions. • The ICS1893 asserts its Collision LED for a period of approximately 70 msec when it detects a collision. Caution: This pin must not float. (See the notes at “ ...
Page 108
... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the address of the ICS1893 when either hardware mode or software mode. – An output pin following reset. In this case, this pin provides link status for the ICS1893 ...
Page 109
... During a reset of the ICS1893, this pins acts as an input. • After a reset of the ICS1893, this pins latches the state of the inputs into their respective PHY Address bits. (See then converts the pin signal to an output that can drive the respective LED directly ...
Page 110
... ICS1893 Data Sheet - Release 9.3.3 Configuration Pins Table 9-4 lists the configuration pins. Table 9-4. Configuration Pins Pin Pin Name Number Type 10/100SEL 2 Input or Output 10TCSR 9 Input 100TCSR 10 Input ANSEL 26 Input or Output DPXSEL 24 Input or Output ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Pin Description 10Base-T / 100Base-TX Select ...
Page 111
... Low, there is no link established. • High, there is a link established. This pin is mapped according to the interface for which the ICS1893 is mapped. For the: • Media Independent Interface (MII), the LSTA is mapped as LSTA. • 100M Symbol Interface, the LSTA is mapped as SD. ...
Page 112
... ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Description Collision (Detect). The ICS1893 asserts a signal on the COL pin when the ICS1893 detects receive activity while transmitting (that is, while the TXEN signal is asserted by the MAC/repeater, that is, when transmitting). When the mode is: • ...
Page 113
... The ICS1893, to transfer status information. All transfers and sampling are synchronous with the signal on the MDC pin. Note: If the ICS1893 used in an application that uses the mechanical MII specification, MDIO must have a 1.5 k pull-up resistor at the ICS1893 end and ±5% pull-down resistor at the station management end ...
Page 114
... Low, the MAC indicates that it is not in a tri-state condition. • High, the MAC indicates that tri-state condition. In this case, the ICS1893 acts to ensure that only one PHY is active at a time. Transmit Clock. The ICS1893 generates this clock signal to synchronize the transfer of data from the MAC/Repeater Interface to the ICS1893. When the mode is: • ...
Page 115
... MII mode: – The ICS1893 synchronously samples its TXER signal on the rising edges of its TXCLK signal. – The assertion of TXER by the MAC/repeater causes the ICS1893 to transmit an Invalid Symbol. – the Invalid Error Code Test bit (bit 16.2) is set to logic one, the 5-bit ...
Page 116
... ICS1893 Data Sheet - Release 9.3.4.2 MAC/Repeater Interface Pins for 100M Symbol Interface Table 9-6 lists the MAC/Repeater Interface pin descriptions for the 100M Symbol Interface. Table 9-6. MAC/Repeater Interface Pins: 100M Symbol Interface MII Pin 100M Pin Name Symbol No. Pin Name COL – 49 CRS ...
Page 117
... Pin Type Output (Symbol) Receive Clock. In Symbol Mode, the ICS1893 sources an SRCLK to a MAC/repeater. The SRCLK synchronizes the signals on the SRD[4:0] pins between the ICS1893 and the MAC/repeater. The following table contrasts the SRCLK behavior when the mode for the ICS1893 is either 10Base-T or 100Base-TX. ...
Page 118
... Low, the MAC indicates it is not in a tri-state condition. • High, the MAC indicates tri-state condition. In this case, the ICS1893 acts to ensure that only one PHY is active at a time. (A PHY address of 00 also tri-states the MII interface.) Output Symbol Transmit Clock. This pin’ ...
Page 119
... Output This pin’ s description is the same as that given in Output 10M Receive Clock. In 10M Serial mode, the ICS1893 sources the 10RCLK to its MAC/repeater Interface. The 10RCLK synchronizes the data on the 10RD0 pin between the ICS1893 and the MAC/repeater. • The 10RCLK frequency is 10 MHz. ...
Page 120
... High, the MAC indicates that tri-state condition. In this case, the ICS1893 acts to ensure that only one PHY is active at a time. • If the PHY address is 00, the ICS1893 acts as if the RX-TRI pin is held high. Output 10M (Serial Interface) Transmit Clock. ...
Page 121
... Pin Pin Name Number Type NC 20 – ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Description No Connect. • This pin is always reserved for use by ICS. • Depending on the interface that is used, some of the MAC/Repeater interface pins can also be no-connects. For pins that are no connects when the interface is the: – ...
Page 122
... ICS1893 Data Sheet - Release 9.3.6 Ground and Power Pins Table 9-9 lists the ground and power pins. Table 9-9. Ground and Power Pins Pin Name Pin Number VSS 4 VSS 11 VSS 12 VSS 17 VSS 22 VSS 28 VSS 29 VSS 40 VSS 56 VSS 57 VSS 58 VSS 61 VDD 7 VDD 8 VDD 15 VDD 16 VDD ...
Page 123
... Stresses above these ratings can permanently damage the ICS1893. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the ICS1893 at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...
Page 124
... Clause 24.2.3.4 is more stringent. It requires the code-bit timer to have an accuracy of 0.005% (that is, ±50 ppm). Note: Although the 10TCSR and 100TCSR pins do not need to be bypassed, include placeholders for bypass capacitors on a printed circuit board that uses the ICS1893. Figure 10-1. ICS1893 10TCSR and 100TCSR VDD ...
Page 125
... Power-Down Supply Current† Reset † These supply current parameters are measured through VDD pins to the ICS1893. The supply current parameters include external transformer currents. ‡ Measurements taken with 100% data transmission and the minimum inter-packet gap. 10.4.2 DC Operating Characteristics for TTL Inputs and Outputs Table 10-5 lists the 3 ...
Page 126
... Parameter Input High Voltage Input Low Voltage 10.4.4 DC Operating Characteristics for Media Independent Interface Table 10-7 lists DC operating characteristics for the Media Independent Interface (MII) for the ICS1893. Table 10-7. DC Operating Characteristics for Media Independent Interface Parameter MII Input Pin Capacitance MII Output Pin Capacitance ...
Page 127
... The REF_IN switching point is 50% of VDD. Table 10-8. REF_IN Timing Time Parameter Period t1 REF_IN Duty Cycle t2 REF_IN Period Figure 10-2. REF_IN Timing Diagram REF_IN ICS1893 Rev C 6/6/00 Chapter 10 DC and AC Operating Conditions Conditions – – Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 127 Figure 10-2 Min. ...
Page 128
... ICS1893 Data Sheet - Release 10.5.2 Timing for Transmit Clock (TXCLK) Pins Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 10-3 shows the timing diagram for the time periods. Table 10-9. Transmit Clock Timing Time ...
Page 129
... RXCLK Period t2c RXCLK Period t2d RXCLK Period Figure 10-4. Receive Clock Timing Diagram t1 RXCLK ICS1893 Rev C 6/6/00 Chapter 10 DC and AC Operating Conditions Conditions – 100M MII (100Base-TX) 10M MII (10Base-T) 100M Symbol Interface (100Base-TX) 10M Serial Interface (10Base-T) t2 Copyright © 2000, Integrated Circuit Systems, Inc. ...
Page 130
... ICS1893 Data Sheet - Release 10.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing Table 10-11 lists the significant time periods for the 100M MII / 100M Stream Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • TXD[3:0] • ...
Page 131
... TXD[3:0], TXEN, TXER Setup to TXCLK Rise t2 TXD[3:0], TXEN, TXER Hold after TXCLK Rise Figure 10-6. 10M MII Synchronous Transmit Timing Diagram TXCLK TXD[3:0] TXEN TXER ICS1893 Rev C 6/6/00 Parameter Conditions t1 t2 Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 131 Chapter 10 DC and AC Operating Conditions Min ...
Page 132
... ICS1893 Data Sheet - Release 10.5.6 MII / 100M Stream Interface: Synchronous Receive Timing Table 10-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the following pins: • RXCLK • RXD[3:0] • RXDV • ...
Page 133
... MDC Period t4 MDC Rise Time to MDIO Valid t5 MDIO Setup Time to MDC t6 MDIO Hold Time after MDC † The ICS1893 is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading of MDC. Figure 10-8. MII Management Interface Timing Diagram MDC t1 MDIO (Output) ...
Page 134
... ICS1893 Data Sheet - Release 10.5.8 10M Serial Interface: Receive Latency Table 10-15 lists the significant time periods for the 10M Serial Interface timing. The time periods consist of timings of signals on the following pins: • TP_RX (the MDI mapping of the 10M/100M MII TP_RXP and TP_RXN pins) • ...
Page 135
... Figure 10-10. 10M MII Receive Latency Timing Diagram † TP_RX RXCLK RXD 5 † Manchester encoding is not shown. ICS1893 Rev C 6/6/00 Parameter Conditions 10M MII 5 t1 Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 135 Chapter 10 DC and AC Operating Conditions Min. Typ. ...
Page 136
... ICS1893 Data Sheet - Release 10.5.10 10M Serial Interface: Transmit Latency Table 10-17 lists the significant time periods for the 10M Serial Interface transmit latency. The time periods consist of timings of signals on the following pins: • 10TXEN (the 10M Serial Interface mapping of the 10M/100M MII TXEN pins) • ...
Page 137
... Figure 10-12. 10M MII Transmit Latency Timing Diagram TXEN TXCLK TXD † TP_TX † Manchester encoding is not shown. ICS1893 Rev C 6/6/00 Parameter Conditions 10M MII Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 137 Chapter 10 DC and AC Operating Conditions Min. ...
Page 138
... ICS1893 Data Sheet - Release 10.5.12 MII / 100M Stream Interface: Transmit Latency Table 10-19 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • TXD (that is, TXD[3:0]) • ...
Page 139
... TXEN Sampled Asserted to CRS Assert t2 TXEN De-Asserted to CRS De-Asserted Figure 10-14. 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) TXEN TXCLK CRS t1 ICS1893 Rev C 6/6/00 Chapter 10 DC and AC Operating Conditions Parameter t2 Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 139 Condi- Min. ...
Page 140
... ICS1893 Data Sheet - Release 10.5.14 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-21 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
Page 141
... Figure 10-16. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram † TP_RX RXCLK RXD † Shown unscrambled. ICS1893 Rev C 6/6/00 Chapter 10 DC and AC Operating Conditions Conditions t1 t2 Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 141 Min. Typ. Max. Units – ...
Page 142
... ICS1893 Data Sheet - Release 10.5.16 100M Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion Table 10-23 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that is, TP_RXP and TP_RXN) • ...
Page 143
... Table 10-24. Power-On Reset Timing Time Period t1 VDD 2 Reset Complete Figure 10-18. Power-On Reset Timing Diagram 2.7 V VDD TXCLK Valid ICS1893 Rev C 6/6/00 Parameter Conditions t1 Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 143 Chapter 10 DC and AC Operating Conditions Min. Typ. Max. – ...
Page 144
... ICS1893 Data Sheet - Release 10.5.18 Reset: Hardware Reset and Power-Down Table 10-25 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • REF_IN • RESETn • TXCLK Figure 10-19 shows the timing diagram for the time periods. ...
Page 145
... TXEN De-Assertion t2 COL Heartbeat Assertion Duration Figure 10-20. 10Base-T Heartbeat (SQE) Timing Diagram TXEN TXCLK COL ICS1893 Rev C 6/6/00 Chapter 10 DC and AC Operating Conditions Section 7.5.10, “ 10Base-T Operation: SQE Conditions 10Base-T Half Duplex 10Base-T Half Duplex t1 t2 Copyright © 2000, Integrated Circuit Systems, Inc. ...
Page 146
... Jabber Activation Time t2 Jabber De-Activation Time Figure 10-21. 10Base-T Jabber Timing Diagram TXEN TP_TX COL ICS1893 Rev C 6/6/00 Chapter 10 DC and AC Operating Conditions Conditions 10Base-T Half Duplex 10Base-T Half Duplex t1 Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 146 Section 7.5.9, “ 10Base-T Operation: Min ...
Page 147
... Time Period t1 Normal Link Pulse Width t2 Normal Link Pulse to Normal Link Pulse Period Figure 10-22. 10Base-T Normal Link Pulse Timing Diagram TP_TXP ICS1893 Rev C 6/6/00 Figure 10-22 shows the timing diagram for the time periods. Parameter Conditions 10Base-T 10Base Copyright © 2000, Integrated Circuit Systems, Inc. ...
Page 148
... ICS1893 Data Sheet - Release 10.5.22 Auto-Negotiation Fast Link Pulse Timing Table 10-29 lists the significant time periods for the ICS1893 Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • TP_TXP • TP_TXN Figure 10-23 shows the timing diagram for one pair of these differential signals, for example TP_TXP minus TP_TXN ...
Page 149
... ICS1893 - Release Chapter 11 Physical Dimensions of ICS1893 Package This section gives the physical dimensions for the ICS1893 package. • The lead count ( leads. • The nominal footprint (that is the body) is 10.0 mm. Table 11-1 lists the ICS1893 physical dimensions, which are shown in Table 11-1. ...
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... Figure 11-1. ICS1893 Physical Dimensions ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ...
Page 151
... ICS1893 - Release Chapter 12 Ordering Information Figure 12-1 shows ordering information for the ICS1893 package: • ICS1893Y-10 Figure 12-1. ICS1893 Ordering Information Y-10 ICS 1893 ICS1893 Rev C 6/6/00 Package Type Y- TQFP (Thin Quad Flat Pack) Device Identifier Company Identifier Integrated Circuit Systems, Inc. Copyright © 2000, Integrated Circuit Systems, Inc. ...
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... Integrated Circuit Systems, Inc. Corporate Headquarters: Silicon Valley: Web Site: ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ...