ICS1893 Integrated Circuit Systems, ICS1893 Datasheet - Page 38

• Manufacturer Part Number: ICS1893
• Description: 3.3-V 10Base-T/100Base-TX Integrated PHYceiver
• Manufacturer: Integrated Circuit Systems

7.1 Functional Block: Media Independent Interface
ICS1893 Rev C 6/6/00
All ICS1893 MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the
ICS1893 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz (for
10Base-T operations).
The Media Independent Interface (MII) consists of two primary components:
1. An interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893). This
2. An interface between the PHY (the ICS1893) and an STA (Station Management entity). The STA-PHY
The ICS1893 Management Register set (discussed in
the following:
•
•
•
Basic Management registers.
As defined in the ISO/IEC 8802-3 standard, these registers include the following:
Extended Management registers.
As defined in the ISO/IEC 8802-3 standard, the ICS1893 supports Extended registers that provide
access to the Organizationally Unique Identifier and all auto-negotiation functionality.
ICS (Vendor-Specific) Management registers.
The ICS1893 provides vendor-specific registers for enhanced PHY operations. Among these is the
QuickPoll Detailed Status Register that provides a comprehensive and consolidated set of real-time PHY
information. Reading the QuickPoll register enables the MAC to obtain comprehensive status data with
a single register access.
– Control Register (register 0), which handles basic device configuration
– Status Register (register 1), which reports basic device capabilities and status
MAC-PHY part of the MII consists of three subcomponents:
a. A synchronous Transmit interface that includes the following signals:
b. A synchronous Receive interface that includes the followings signals:
c. A Media Status or Control interface that consists of a Carrier Sense signal (CRS) and a Collision
part of the MII is a two-wire, Serial Management Interface that consists of the following:
a. A clock (MDC)
b. A synchronous, bi-directional data signal (MDIO) that provides an STA with access to the ICS1893
ICS1893 Data Sheet - Release
Detection signal (COL).
Management Register set
(1) A data nibble, TXD[3:0]
(2) An error indicator, TXER
(3) A delimiter, TXEN
(4) A clock, TXCLK
(1) A data nibble, RXD[3:0]
(2) An error indicator, RXER
(3) A delimiter, RXDV
(4) A clock, RXCLK
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
38
Chapter 8, “ Management Register Set”
Chapter 7 Functional Blocks
) consists of
June, 2000