C8051F000DK-E Silicon Laboratories Inc, C8051F000DK-E Datasheet - Page 131

• Manufacturer Part Number: C8051F000DK-E
• Description: DEV KIT FOR C8051F000/F001/F002
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F000DK-E

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

18.1.
The UART provides four operating modes (one synchronous and three asynchronous) selected by setting
configuration bits in the SCON register. These four modes offer different baud rates and communication protocols.
The four modes are summarized in Table 18.1 below. Detailed descriptions follow.
18.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the RX pin.
The TX pin provides the shift clock for both transmit and receive. The MCU must be the master since it generates
the shift clock for transmission in both directions (see the interconnect diagram in Figure 18.2).
Eight data bits are transmitted/received, LSB first (see the timing diagram in Figure 18.3). Data transmission begins
when an instruction writes a data byte to the SBUF register. The TI Transmit Interrupt Flag (SCON.1) is set at the
end of the eighth bit time. Data reception begins when the REN Receive Enable bit (SCON.4) is set to logic 1 and
the RI Receive Interrupt Flag (SCON.0) is cleared. One cycle after the eighth bit is shifted in, the RI flag is set and
reception stops until software clears the RI bit. An interrupt will occur if enabled when either TI or RI is set.
The Mode 0 baud rate is the system clock frequency divided by twelve. RX is forced to open-drain in mode 0, and
an external pull-up will typically be required.
18.1.2. Mode 1: 8-Bit UART, Variable Baud Rate
131
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Mode
0
1
2
3
UART Operational Modes
RX (data out)
RX (data in)
TX (clk out)
TX (clk out)
Synchronization
Asynchronous
Asynchronous
Asynchronous
Synchronous
Figure 18.3. UART Mode 0 Timing Diagram
C8051Fxxx
Figure 18.2. UART Mode 0 Interconnect
D0
D0
Timer 1 or Timer 2 Overflow
Timer 1 or Timer 2 Overflow
SYSCLK/32 or SYSCLK/64
Table 18.1. UART Modes
D1
RX
TX
D1
SYSCLK/12
Baud Clock
MODE 0 TRANSMIT
MODE 0 RECEIVE
Rev. 1.7
D2
D2
D3
CLK
DATA
D3
8 Extra Outputs
D4
D4
Data Bits
Reg.
Shift
D5
8
8
9
9
D5
D6
Start/Stop Bits
1 Start, 1 Stop
1 Start, 1 Stop
1 Start, 1 Stop
D6
None
D7
D7